* [PATCH] target/riscv/kvm: Fix leak of reg list
@ 2024-11-04 17:35 Andrew Jones
2024-11-04 17:43 ` Daniel Henrique Barboza
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Andrew Jones @ 2024-11-04 17:35 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: palmer, alistair.francis, bmeng.cn, Daniel Henrique Barboza
Free the temporary register list.
Fixes: 608bdebb6075 ("target/riscv/kvm: support KVM_GET_REG_LIST")
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
---
target/riscv/kvm/kvm-cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index cbda4596da73..effd8fed815d 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -1170,6 +1170,8 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
}
kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
+
+ g_free(reglist);
}
static void riscv_init_kvm_registers(Object *cpu_obj)
--
2.47.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv/kvm: Fix leak of reg list
2024-11-04 17:35 [PATCH] target/riscv/kvm: Fix leak of reg list Andrew Jones
@ 2024-11-04 17:43 ` Daniel Henrique Barboza
2024-11-04 22:59 ` Alistair Francis
2024-11-04 23:03 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Daniel Henrique Barboza @ 2024-11-04 17:43 UTC (permalink / raw)
To: Andrew Jones, qemu-devel, qemu-riscv; +Cc: palmer, alistair.francis, bmeng.cn
On 11/4/24 2:35 PM, Andrew Jones wrote:
> Free the temporary register list.
>
> Fixes: 608bdebb6075 ("target/riscv/kvm: support KVM_GET_REG_LIST")
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/kvm/kvm-cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index cbda4596da73..effd8fed815d 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -1170,6 +1170,8 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
> }
>
> kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
> +
> + g_free(reglist);
> }
>
> static void riscv_init_kvm_registers(Object *cpu_obj)
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv/kvm: Fix leak of reg list
2024-11-04 17:35 [PATCH] target/riscv/kvm: Fix leak of reg list Andrew Jones
2024-11-04 17:43 ` Daniel Henrique Barboza
@ 2024-11-04 22:59 ` Alistair Francis
2024-11-04 23:03 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2024-11-04 22:59 UTC (permalink / raw)
To: Andrew Jones
Cc: qemu-devel, qemu-riscv, palmer, alistair.francis, bmeng.cn,
Daniel Henrique Barboza
On Tue, Nov 5, 2024 at 3:36 AM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> Free the temporary register list.
>
> Fixes: 608bdebb6075 ("target/riscv/kvm: support KVM_GET_REG_LIST")
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/kvm/kvm-cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index cbda4596da73..effd8fed815d 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -1170,6 +1170,8 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
> }
>
> kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
> +
> + g_free(reglist);
> }
>
> static void riscv_init_kvm_registers(Object *cpu_obj)
> --
> 2.47.0
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] target/riscv/kvm: Fix leak of reg list
2024-11-04 17:35 [PATCH] target/riscv/kvm: Fix leak of reg list Andrew Jones
2024-11-04 17:43 ` Daniel Henrique Barboza
2024-11-04 22:59 ` Alistair Francis
@ 2024-11-04 23:03 ` Alistair Francis
2 siblings, 0 replies; 4+ messages in thread
From: Alistair Francis @ 2024-11-04 23:03 UTC (permalink / raw)
To: Andrew Jones
Cc: qemu-devel, qemu-riscv, palmer, alistair.francis, bmeng.cn,
Daniel Henrique Barboza
On Tue, Nov 5, 2024 at 3:36 AM Andrew Jones <ajones@ventanamicro.com> wrote:
>
> Free the temporary register list.
>
> Fixes: 608bdebb6075 ("target/riscv/kvm: support KVM_GET_REG_LIST")
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/kvm/kvm-cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index cbda4596da73..effd8fed815d 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -1170,6 +1170,8 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
> }
>
> kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
> +
> + g_free(reglist);
> }
>
> static void riscv_init_kvm_registers(Object *cpu_obj)
> --
> 2.47.0
>
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2024-11-04 23:04 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2024-11-04 17:35 [PATCH] target/riscv/kvm: Fix leak of reg list Andrew Jones
2024-11-04 17:43 ` Daniel Henrique Barboza
2024-11-04 22:59 ` Alistair Francis
2024-11-04 23:03 ` Alistair Francis
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