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From: "Heiko Stübner" <heiko@sntech.de>
To: Xing Zheng <zhengxing@rock-chips.com>
Cc: linux-rockchip@lists.infradead.org, huangtao@rock-chips.com,
	jay.xu@rock-chips.com, elaine.zhang@rock-chips.com,
	dianders@chromium.org,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/7] clk: rockchip: add more mux parameters for new pll sources
Date: Wed, 09 Mar 2016 17:50:17 +0100	[thread overview]
Message-ID: <6921896.5phntn5YJn@diego> (raw)
In-Reply-To: <1457491027-30936-4-git-send-email-zhengxing@rock-chips.com>

Am Mittwoch, 9. M=E4rz 2016, 10:37:03 schrieb Xing Zheng:
> Thers are only two parent PLLs that APLL and GPLL for core on the
> previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
> GPLL as alternate parent when core is switching freq.
>=20
> Since RK3399 big.LITTLE architecture, we need to select and adapt
> more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.
>=20
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

applied to my clk-branch for v4.7, with an adapted subject of
"clk: rockchip: allow varying mux parameters for cpuclk pll-sources"


Thanks
Heiko

WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: Xing Zheng <zhengxing@rock-chips.com>
Cc: linux-rockchip@lists.infradead.org, huangtao@rock-chips.com,
	jay.xu@rock-chips.com, elaine.zhang@rock-chips.com,
	dianders@chromium.org,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/7] clk: rockchip: add more mux parameters for new pll sources
Date: Wed, 09 Mar 2016 17:50:17 +0100	[thread overview]
Message-ID: <6921896.5phntn5YJn@diego> (raw)
In-Reply-To: <1457491027-30936-4-git-send-email-zhengxing@rock-chips.com>

Am Mittwoch, 9. März 2016, 10:37:03 schrieb Xing Zheng:
> Thers are only two parent PLLs that APLL and GPLL for core on the
> previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
> GPLL as alternate parent when core is switching freq.
> 
> Since RK3399 big.LITTLE architecture, we need to select and adapt
> more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.
> 
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

applied to my clk-branch for v4.7, with an adapted subject of
"clk: rockchip: allow varying mux parameters for cpuclk pll-sources"


Thanks
Heiko

WARNING: multiple messages have this Message-ID (diff)
From: heiko@sntech.de (Heiko Stübner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 3/7] clk: rockchip: add more mux parameters for new pll sources
Date: Wed, 09 Mar 2016 17:50:17 +0100	[thread overview]
Message-ID: <6921896.5phntn5YJn@diego> (raw)
In-Reply-To: <1457491027-30936-4-git-send-email-zhengxing@rock-chips.com>

Am Mittwoch, 9. M?rz 2016, 10:37:03 schrieb Xing Zheng:
> Thers are only two parent PLLs that APLL and GPLL for core on the
> previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
> GPLL as alternate parent when core is switching freq.
> 
> Since RK3399 big.LITTLE architecture, we need to select and adapt
> more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.
> 
> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

applied to my clk-branch for v4.7, with an adapted subject of
"clk: rockchip: allow varying mux parameters for cpuclk pll-sources"


Thanks
Heiko

  reply	other threads:[~2016-03-09 16:50 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-09  2:37 [PATCH v3 0/7] Add more clock compatible features and support the RK3399 clock Xing Zheng
2016-03-09  2:37 ` Xing Zheng
     [not found] ` <1457491027-30936-1-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-03-09  2:37   ` [PATCH v3 1/7] dt-bindings: add bindings for rk3399 clock controller Xing Zheng
2016-03-09  2:37     ` Xing Zheng
2016-03-09  2:37     ` Xing Zheng
2016-03-09  2:37 ` [PATCH v3 2/7] clk: rockchip: add dt-binding header for rk3399 Xing Zheng
2016-03-09  2:37 ` [PATCH v3 3/7] clk: rockchip: add more mux parameters for new pll sources Xing Zheng
2016-03-09  2:37   ` Xing Zheng
2016-03-09 16:50   ` Heiko Stübner [this message]
2016-03-09 16:50     ` Heiko Stübner
2016-03-09 16:50     ` Heiko Stübner
2016-03-09  2:37 ` [PATCH v3 4/7] clk: rockchip: Add support for multiple clock providers Xing Zheng
2016-03-09  2:37   ` Xing Zheng
2016-03-09 22:25   ` Heiko Stübner
2016-03-09 22:25     ` Heiko Stübner
2016-03-09 22:25     ` Heiko Stübner
2016-03-10  2:29     ` Xing Zheng
2016-03-10  2:29       ` Xing Zheng
2016-03-09  2:42 ` [PATCH v3 5/7] clk: rockchip: add new pll-type for rk3399 and similar socs Xing Zheng
2016-03-09  2:42   ` Xing Zheng
2016-03-09 12:29   ` Heiko Stübner
2016-03-09 12:29     ` Heiko Stübner
2016-03-09 12:29     ` Heiko Stübner
2016-03-10  3:25     ` Xing Zheng
2016-03-10  3:25       ` Xing Zheng
2016-03-09  2:43 ` [PATCH v3 6/7] clk: rockchip: add a COMPOSITE_FRACMUX_NOGATE type Xing Zheng
2016-03-09  2:43   ` Xing Zheng
2016-03-09 12:35   ` Heiko Stübner
2016-03-09 12:35     ` Heiko Stübner
2016-03-09 12:35     ` Heiko Stübner
2016-03-09  2:44 ` [PATCH v3 7/7] clk: rockchip: add clock controller for the RK3399 Xing Zheng
2016-03-09  2:44   ` Xing Zheng

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