From: "Heiko Stübner" <heiko@sntech.de>
To: Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>, Alex Bee <knaerzche@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@gmail.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
Maxime Ripard <mripard@kernel.org>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org,
Alex Bee <knaerzche@gmail.com>
Subject: Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128
Date: Sat, 02 Dec 2023 16:51:56 +0100 [thread overview]
Message-ID: <6926340.F8r316W7xa@diego> (raw)
In-Reply-To: <20231202125144.66052-3-knaerzche@gmail.com>
Hi Alex,
Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> Add power controller and qos nodes for RK3128 in order to use
> them as powerdomains.
does the power-domain controller work with the incomplete set of
pm-domains too?
What I have in mind is
- adding the power-controller node with the existing set of power-domains
- the gpu pm-domain is in there
- adding the gpu parts
And a second series with
- patch1 from here
- a dts patch adding the additional pm-domains to rk3128.dtsi
- I guess patch1 also should be split into a patch adding the binding-ids
and a separate patch for the code addition.
Heiko
> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
> arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
> 1 file changed, 101 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> index 4e8b38604ecd..b72905db04f7 100644
> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/power/rk3128-power.h>
>
> / {
> compatible = "rockchip,rk3128";
> @@ -133,6 +134,106 @@ smp-sram@0 {
> pmu: syscon@100a0000 {
> compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> reg = <0x100a0000 0x1000>;
> +
> + power: power-controller {
> + compatible = "rockchip,rk3128-power-controller";
> + #power-domain-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + power-domain@RK3128_PD_VIO {
> + reg = <RK3128_PD_VIO>;
> + clocks = <&cru ACLK_CIF>,
> + <&cru HCLK_CIF>,
> + <&cru DCLK_EBC>,
> + <&cru HCLK_EBC>,
> + <&cru ACLK_IEP>,
> + <&cru HCLK_IEP>,
> + <&cru ACLK_LCDC0>,
> + <&cru HCLK_LCDC0>,
> + <&cru PCLK_MIPI>,
> + <&cru ACLK_RGA>,
> + <&cru HCLK_RGA>,
> + <&cru ACLK_VIO0>,
> + <&cru ACLK_VIO1>,
> + <&cru HCLK_VIO>,
> + <&cru HCLK_VIO_H2P>,
> + <&cru DCLK_VOP>,
> + <&cru SCLK_VOP>;
> + pm_qos = <&qos_ebc>,
> + <&qos_iep>,
> + <&qos_lcdc>,
> + <&qos_rga>,
> + <&qos_vip>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_VIDEO {
> + reg = <RK3128_PD_VIDEO>;
> + clocks = <&cru ACLK_VDPU>,
> + <&cru HCLK_VDPU>,
> + <&cru ACLK_VEPU>,
> + <&cru HCLK_VEPU>,
> + <&cru SCLK_HEVC_CORE>;
> + pm_qos = <&qos_vpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_GPU {
> + reg = <RK3128_PD_GPU>;
> + clocks = <&cru ACLK_GPU>;
> + pm_qos = <&qos_gpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_CRYPTO {
> + reg = <RK3128_PD_CRYPTO>;
> + clocks = <&cru HCLK_CRYPTO>,
> + <&cru SCLK_CRYPTO>;
> + pm_qos = <&qos_crypto>;
> + #power-domain-cells = <0>;
> + };
> + };
> + };
> +
> + qos_crypto: qos@10128080 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x10128080 0x20>;
> + };
> +
> + qos_gpu: qos@1012d000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012d000 0x20>;
> + };
> +
> + qos_vpu: qos@1012e000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012e000 0x20>;
> + };
> +
> + qos_rga: qos@1012f000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f000 0x20>;
> + };
> +
> + qos_ebc: qos@1012f080 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f080 0x20>;
> + };
> +
> + qos_iep: qos@1012f100 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f100 0x20>;
> + };
> +
> + qos_lcdc: qos@1012f180 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f180 0x20>;
> + };
> +
> + qos_vip: qos@1012f200 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f200 0x20>;
> };
>
> gic: interrupt-controller@10139000 {
>
WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>, Alex Bee <knaerzche@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@gmail.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
Maxime Ripard <mripard@kernel.org>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org,
Alex Bee <knaerzche@gmail.com>
Subject: Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128
Date: Sat, 02 Dec 2023 16:51:56 +0100 [thread overview]
Message-ID: <6926340.F8r316W7xa@diego> (raw)
In-Reply-To: <20231202125144.66052-3-knaerzche@gmail.com>
Hi Alex,
Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> Add power controller and qos nodes for RK3128 in order to use
> them as powerdomains.
does the power-domain controller work with the incomplete set of
pm-domains too?
What I have in mind is
- adding the power-controller node with the existing set of power-domains
- the gpu pm-domain is in there
- adding the gpu parts
And a second series with
- patch1 from here
- a dts patch adding the additional pm-domains to rk3128.dtsi
- I guess patch1 also should be split into a patch adding the binding-ids
and a separate patch for the code addition.
Heiko
> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
> arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
> 1 file changed, 101 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> index 4e8b38604ecd..b72905db04f7 100644
> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/power/rk3128-power.h>
>
> / {
> compatible = "rockchip,rk3128";
> @@ -133,6 +134,106 @@ smp-sram@0 {
> pmu: syscon@100a0000 {
> compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> reg = <0x100a0000 0x1000>;
> +
> + power: power-controller {
> + compatible = "rockchip,rk3128-power-controller";
> + #power-domain-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + power-domain@RK3128_PD_VIO {
> + reg = <RK3128_PD_VIO>;
> + clocks = <&cru ACLK_CIF>,
> + <&cru HCLK_CIF>,
> + <&cru DCLK_EBC>,
> + <&cru HCLK_EBC>,
> + <&cru ACLK_IEP>,
> + <&cru HCLK_IEP>,
> + <&cru ACLK_LCDC0>,
> + <&cru HCLK_LCDC0>,
> + <&cru PCLK_MIPI>,
> + <&cru ACLK_RGA>,
> + <&cru HCLK_RGA>,
> + <&cru ACLK_VIO0>,
> + <&cru ACLK_VIO1>,
> + <&cru HCLK_VIO>,
> + <&cru HCLK_VIO_H2P>,
> + <&cru DCLK_VOP>,
> + <&cru SCLK_VOP>;
> + pm_qos = <&qos_ebc>,
> + <&qos_iep>,
> + <&qos_lcdc>,
> + <&qos_rga>,
> + <&qos_vip>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_VIDEO {
> + reg = <RK3128_PD_VIDEO>;
> + clocks = <&cru ACLK_VDPU>,
> + <&cru HCLK_VDPU>,
> + <&cru ACLK_VEPU>,
> + <&cru HCLK_VEPU>,
> + <&cru SCLK_HEVC_CORE>;
> + pm_qos = <&qos_vpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_GPU {
> + reg = <RK3128_PD_GPU>;
> + clocks = <&cru ACLK_GPU>;
> + pm_qos = <&qos_gpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_CRYPTO {
> + reg = <RK3128_PD_CRYPTO>;
> + clocks = <&cru HCLK_CRYPTO>,
> + <&cru SCLK_CRYPTO>;
> + pm_qos = <&qos_crypto>;
> + #power-domain-cells = <0>;
> + };
> + };
> + };
> +
> + qos_crypto: qos@10128080 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x10128080 0x20>;
> + };
> +
> + qos_gpu: qos@1012d000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012d000 0x20>;
> + };
> +
> + qos_vpu: qos@1012e000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012e000 0x20>;
> + };
> +
> + qos_rga: qos@1012f000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f000 0x20>;
> + };
> +
> + qos_ebc: qos@1012f080 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f080 0x20>;
> + };
> +
> + qos_iep: qos@1012f100 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f100 0x20>;
> + };
> +
> + qos_lcdc: qos@1012f180 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f180 0x20>;
> + };
> +
> + qos_vip: qos@1012f200 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f200 0x20>;
> };
>
> gic: interrupt-controller@10139000 {
>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>, Alex Bee <knaerzche@gmail.com>
Cc: Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@gmail.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
Maxime Ripard <mripard@kernel.org>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-pm@vger.kernel.org,
Alex Bee <knaerzche@gmail.com>
Subject: Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128
Date: Sat, 02 Dec 2023 16:51:56 +0100 [thread overview]
Message-ID: <6926340.F8r316W7xa@diego> (raw)
In-Reply-To: <20231202125144.66052-3-knaerzche@gmail.com>
Hi Alex,
Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> Add power controller and qos nodes for RK3128 in order to use
> them as powerdomains.
does the power-domain controller work with the incomplete set of
pm-domains too?
What I have in mind is
- adding the power-controller node with the existing set of power-domains
- the gpu pm-domain is in there
- adding the gpu parts
And a second series with
- patch1 from here
- a dts patch adding the additional pm-domains to rk3128.dtsi
- I guess patch1 also should be split into a patch adding the binding-ids
and a separate patch for the code addition.
Heiko
> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
> arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
> 1 file changed, 101 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> index 4e8b38604ecd..b72905db04f7 100644
> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/power/rk3128-power.h>
>
> / {
> compatible = "rockchip,rk3128";
> @@ -133,6 +134,106 @@ smp-sram@0 {
> pmu: syscon@100a0000 {
> compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> reg = <0x100a0000 0x1000>;
> +
> + power: power-controller {
> + compatible = "rockchip,rk3128-power-controller";
> + #power-domain-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + power-domain@RK3128_PD_VIO {
> + reg = <RK3128_PD_VIO>;
> + clocks = <&cru ACLK_CIF>,
> + <&cru HCLK_CIF>,
> + <&cru DCLK_EBC>,
> + <&cru HCLK_EBC>,
> + <&cru ACLK_IEP>,
> + <&cru HCLK_IEP>,
> + <&cru ACLK_LCDC0>,
> + <&cru HCLK_LCDC0>,
> + <&cru PCLK_MIPI>,
> + <&cru ACLK_RGA>,
> + <&cru HCLK_RGA>,
> + <&cru ACLK_VIO0>,
> + <&cru ACLK_VIO1>,
> + <&cru HCLK_VIO>,
> + <&cru HCLK_VIO_H2P>,
> + <&cru DCLK_VOP>,
> + <&cru SCLK_VOP>;
> + pm_qos = <&qos_ebc>,
> + <&qos_iep>,
> + <&qos_lcdc>,
> + <&qos_rga>,
> + <&qos_vip>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_VIDEO {
> + reg = <RK3128_PD_VIDEO>;
> + clocks = <&cru ACLK_VDPU>,
> + <&cru HCLK_VDPU>,
> + <&cru ACLK_VEPU>,
> + <&cru HCLK_VEPU>,
> + <&cru SCLK_HEVC_CORE>;
> + pm_qos = <&qos_vpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_GPU {
> + reg = <RK3128_PD_GPU>;
> + clocks = <&cru ACLK_GPU>;
> + pm_qos = <&qos_gpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_CRYPTO {
> + reg = <RK3128_PD_CRYPTO>;
> + clocks = <&cru HCLK_CRYPTO>,
> + <&cru SCLK_CRYPTO>;
> + pm_qos = <&qos_crypto>;
> + #power-domain-cells = <0>;
> + };
> + };
> + };
> +
> + qos_crypto: qos@10128080 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x10128080 0x20>;
> + };
> +
> + qos_gpu: qos@1012d000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012d000 0x20>;
> + };
> +
> + qos_vpu: qos@1012e000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012e000 0x20>;
> + };
> +
> + qos_rga: qos@1012f000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f000 0x20>;
> + };
> +
> + qos_ebc: qos@1012f080 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f080 0x20>;
> + };
> +
> + qos_iep: qos@1012f100 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f100 0x20>;
> + };
> +
> + qos_lcdc: qos@1012f180 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f180 0x20>;
> + };
> +
> + qos_vip: qos@1012f200 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f200 0x20>;
> };
>
> gic: interrupt-controller@10139000 {
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Rob Herring <robh+dt@kernel.org>, Alex Bee <knaerzche@gmail.com>
Cc: devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org, Maxime Ripard <mripard@kernel.org>,
Alex Bee <knaerzche@gmail.com>,
linux-rockchip@lists.infradead.org,
dri-devel@lists.freedesktop.org,
Thomas Zimmermann <tzimmermann@suse.de>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller for RK3128
Date: Sat, 02 Dec 2023 16:51:56 +0100 [thread overview]
Message-ID: <6926340.F8r316W7xa@diego> (raw)
In-Reply-To: <20231202125144.66052-3-knaerzche@gmail.com>
Hi Alex,
Am Samstag, 2. Dezember 2023, 13:51:41 CET schrieb Alex Bee:
> Add power controller and qos nodes for RK3128 in order to use
> them as powerdomains.
does the power-domain controller work with the incomplete set of
pm-domains too?
What I have in mind is
- adding the power-controller node with the existing set of power-domains
- the gpu pm-domain is in there
- adding the gpu parts
And a second series with
- patch1 from here
- a dts patch adding the additional pm-domains to rk3128.dtsi
- I guess patch1 also should be split into a patch adding the binding-ids
and a separate patch for the code addition.
Heiko
> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> ---
> arch/arm/boot/dts/rockchip/rk3128.dtsi | 101 +++++++++++++++++++++++++
> 1 file changed, 101 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> index 4e8b38604ecd..b72905db04f7 100644
> --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
> +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
> @@ -8,6 +8,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/power/rk3128-power.h>
>
> / {
> compatible = "rockchip,rk3128";
> @@ -133,6 +134,106 @@ smp-sram@0 {
> pmu: syscon@100a0000 {
> compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd";
> reg = <0x100a0000 0x1000>;
> +
> + power: power-controller {
> + compatible = "rockchip,rk3128-power-controller";
> + #power-domain-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + power-domain@RK3128_PD_VIO {
> + reg = <RK3128_PD_VIO>;
> + clocks = <&cru ACLK_CIF>,
> + <&cru HCLK_CIF>,
> + <&cru DCLK_EBC>,
> + <&cru HCLK_EBC>,
> + <&cru ACLK_IEP>,
> + <&cru HCLK_IEP>,
> + <&cru ACLK_LCDC0>,
> + <&cru HCLK_LCDC0>,
> + <&cru PCLK_MIPI>,
> + <&cru ACLK_RGA>,
> + <&cru HCLK_RGA>,
> + <&cru ACLK_VIO0>,
> + <&cru ACLK_VIO1>,
> + <&cru HCLK_VIO>,
> + <&cru HCLK_VIO_H2P>,
> + <&cru DCLK_VOP>,
> + <&cru SCLK_VOP>;
> + pm_qos = <&qos_ebc>,
> + <&qos_iep>,
> + <&qos_lcdc>,
> + <&qos_rga>,
> + <&qos_vip>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_VIDEO {
> + reg = <RK3128_PD_VIDEO>;
> + clocks = <&cru ACLK_VDPU>,
> + <&cru HCLK_VDPU>,
> + <&cru ACLK_VEPU>,
> + <&cru HCLK_VEPU>,
> + <&cru SCLK_HEVC_CORE>;
> + pm_qos = <&qos_vpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_GPU {
> + reg = <RK3128_PD_GPU>;
> + clocks = <&cru ACLK_GPU>;
> + pm_qos = <&qos_gpu>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RK3128_PD_CRYPTO {
> + reg = <RK3128_PD_CRYPTO>;
> + clocks = <&cru HCLK_CRYPTO>,
> + <&cru SCLK_CRYPTO>;
> + pm_qos = <&qos_crypto>;
> + #power-domain-cells = <0>;
> + };
> + };
> + };
> +
> + qos_crypto: qos@10128080 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x10128080 0x20>;
> + };
> +
> + qos_gpu: qos@1012d000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012d000 0x20>;
> + };
> +
> + qos_vpu: qos@1012e000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012e000 0x20>;
> + };
> +
> + qos_rga: qos@1012f000 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f000 0x20>;
> + };
> +
> + qos_ebc: qos@1012f080 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f080 0x20>;
> + };
> +
> + qos_iep: qos@1012f100 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f100 0x20>;
> + };
> +
> + qos_lcdc: qos@1012f180 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f180 0x20>;
> + };
> +
> + qos_vip: qos@1012f200 {
> + compatible = "rockchip,rk3128-qos", "syscon";
> + reg = <0x1012f200 0x20>;
> };
>
> gic: interrupt-controller@10139000 {
>
next prev parent reply other threads:[~2023-12-02 15:52 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-02 12:51 [PATCH v2 0/5] Add power-controller and gpu for RK3128 Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` [PATCH v2 1/5] pmdomain: rockchip: Add missing powerdomains " Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-08 15:29 ` Rob Herring
2023-12-08 15:29 ` Rob Herring
2023-12-08 15:29 ` Rob Herring
2023-12-08 15:29 ` Rob Herring
2023-12-02 12:51 ` [PATCH v2 2/5] ARM: dts: rockchip: Add power-controller " Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 15:51 ` Heiko Stübner [this message]
2023-12-02 15:51 ` Heiko Stübner
2023-12-02 15:51 ` Heiko Stübner
2023-12-02 15:51 ` Heiko Stübner
2023-12-02 16:36 ` Alex Bee
2023-12-02 16:36 ` Alex Bee
2023-12-02 16:36 ` Alex Bee
2023-12-02 16:36 ` Alex Bee
2023-12-02 17:46 ` Heiko Stübner
2023-12-02 17:46 ` Heiko Stübner
2023-12-02 17:46 ` Heiko Stübner
2023-12-02 17:46 ` Heiko Stübner
2023-12-03 16:05 ` Alex Bee
2023-12-03 16:05 ` Alex Bee
2023-12-03 16:05 ` Alex Bee
2023-12-03 16:05 ` Alex Bee
2023-12-03 16:42 ` Heiko Stübner
2023-12-03 16:42 ` Heiko Stübner
2023-12-03 16:42 ` Heiko Stübner
2023-12-03 16:42 ` Heiko Stübner
2023-12-04 15:23 ` Alex Bee
2023-12-04 15:23 ` Alex Bee
2023-12-04 15:23 ` Alex Bee
2023-12-04 15:23 ` Alex Bee
2023-12-02 12:51 ` [PATCH v2 3/5] dt-bindings: gpu: mali-utgard: Add Rockchip RK3128 compatible Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` [PATCH v2 4/5] ARM: dts: rockchip: Add GPU node for RK3128 Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` [PATCH v2 5/5] ARM: dts: rockchip: Enable GPU for XPI-3128 Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 12:51 ` Alex Bee
2023-12-02 15:57 ` (subset) [PATCH v2 0/5] Add power-controller and gpu for RK3128 Heiko Stuebner
2023-12-02 15:57 ` Heiko Stuebner
2023-12-02 15:57 ` Heiko Stuebner
2023-12-02 15:57 ` Heiko Stuebner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=6926340.F8r316W7xa@diego \
--to=heiko@sntech.de \
--cc=airlied@gmail.com \
--cc=conor+dt@kernel.org \
--cc=daniel@ffwll.ch \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=knaerzche@gmail.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=maarten.lankhorst@linux.intel.com \
--cc=mripard@kernel.org \
--cc=robh+dt@kernel.org \
--cc=tzimmermann@suse.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.