* [PATCH] target/riscv: gate envcfg CBO fields on extensions
@ 2026-10-15 3:11 wangyang
0 siblings, 0 replies; 3+ messages in thread
From: wangyang @ 2026-10-15 3:11 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, Palmer Dabbelt, Alistair Francis,
Daniel Henrique Barboza, Liu Zhiwei
The envcfg CBO fields are provided by Zicbom and Zicboz. Keep them
read-only zero when the corresponding extension is absent in all three
envcfg CSRs.
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4225
Signed-off-by: wangyang <wangyang25@otcaix.iscas.ac.cn>
---
target/riscv/tcg/csr.c | 25 ++++++++++++++++++++++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index 061bc9d..ba68c25 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -3224,10 +3224,19 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
- uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE |
- MENVCFG_CBZE;
+ uint64_t mask = MENVCFG_FIOM;
bool stce_changed = false;
+ /* CBIE/CBCFE are read-only zero when Zicbom is not implemented. */
+ if (cfg->ext_zicbom) {
+ mask |= MENVCFG_CBIE | MENVCFG_CBCFE;
+ }
+
+ /* CBZE is read-only zero when Zicboz is not implemented. */
+ if (cfg->ext_zicboz) {
+ mask |= MENVCFG_CBZE;
+ }
+
/*
* menvcfg.LPE (Zicfilp) and menvcfg.SSE (Zicfiss) reside in the low
* 32 bits and are defined for both RV32 and RV64, so they must be
@@ -3386,10 +3395,20 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
- uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
+ uint64_t mask = HENVCFG_FIOM;
RISCVException ret;
bool stce_changed = false;
+ /* CBIE/CBCFE are read-only zero when Zicbom is not implemented. */
+ if (cfg->ext_zicbom) {
+ mask |= HENVCFG_CBIE | HENVCFG_CBCFE;
+ }
+
+ /* CBZE is read-only zero when Zicboz is not implemented. */
+ if (cfg->ext_zicboz) {
+ mask |= HENVCFG_CBZE;
+ }
+
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
if (ret != RISCV_EXCP_NONE) {
return ret;
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH] target/riscv: gate envcfg CBO fields on extensions
@ 2026-10-15 7:53 wangyang
0 siblings, 0 replies; 3+ messages in thread
From: wangyang @ 2026-10-15 7:53 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
The envcfg CBO fields are provided by Zicbom and Zicboz. Keep them
read-only zero when the corresponding extension is absent in all three
envcfg CSRs.
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4225
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: wangyang <wangyang25@otcaix.iscas.ac.cn>
target/riscv/tcg/csr.c | 37 +++++++++++++++++++++++++++++++++----
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index 061bc9d..96c513b 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -3224,10 +3224,19 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
- uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE |
- MENVCFG_CBZE;
+ uint64_t mask = MENVCFG_FIOM;
bool stce_changed = false;
+ /* CBIE/CBCFE are read-only zero when Zicbom is not implemented. */
+ if (cfg->ext_zicbom) {
+ mask |= MENVCFG_CBIE | MENVCFG_CBCFE;
+ }
+
+ /* CBZE is read-only zero when Zicboz is not implemented. */
+ if (cfg->ext_zicboz) {
+ mask |= MENVCFG_CBZE;
+ }
+
/*
* menvcfg.LPE (Zicfilp) and menvcfg.SSE (Zicfiss) reside in the low
* 32 bits and are defined for both RV32 and RV64, so they must be
@@ -3328,8 +3337,18 @@ static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
- uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
+ uint64_t mask = SENVCFG_FIOM;
RISCVException ret;
+
+ /* CBIE/CBCFE are read-only zero when Zicbom is not implemented. */
+ if (env_archcpu(env)->cfg.ext_zicbom) {
+ mask |= SENVCFG_CBIE | SENVCFG_CBCFE;
+ }
+
+ /* CBZE is read-only zero when Zicboz is not implemented. */
+ if (env_archcpu(env)->cfg.ext_zicboz) {
+ mask |= SENVCFG_CBZE;
+ }
/* Update PMM field only if the value is valid according to Zjpm v1.0 */
if (env_archcpu(env)->cfg.ext_ssnpm &&
riscv_cpu_mxl(env) == MXL_RV64 &&
@@ -3386,10 +3405,20 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
- uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
+ uint64_t mask = HENVCFG_FIOM;
RISCVException ret;
bool stce_changed = false;
+ /* CBIE/CBCFE are read-only zero when Zicbom is not implemented. */
+ if (cfg->ext_zicbom) {
+ mask |= HENVCFG_CBIE | HENVCFG_CBCFE;
+ }
+
+ /* CBZE is read-only zero when Zicboz is not implemented. */
+ if (cfg->ext_zicboz) {
+ mask |= HENVCFG_CBZE;
+ }
+
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
if (ret != RISCV_EXCP_NONE) {
return ret;
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH] target/riscv: gate envcfg CBO fields on extensions
@ 2026-10-15 8:05 wangyang
0 siblings, 0 replies; 3+ messages in thread
From: wangyang @ 2026-10-15 8:05 UTC (permalink / raw)
To: qemu-devel
Cc: qemu-riscv, Palmer Dabbelt, Alistair Francis, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei
The envcfg CBO fields are provided by Zicbom and Zicboz. Keep them
read-only zero when the corresponding extension is absent in all three
envcfg CSRs.
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4225
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: wangyang <wangyang25@otcaix.iscas.ac.cn>
---
target/riscv/tcg/csr.c | 37 +++++++++++++++++++++++++++++++++----
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index 061bc9d..96c513b 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -3224,10 +3224,19 @@ static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
- uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE |
- MENVCFG_CBZE;
+ uint64_t mask = MENVCFG_FIOM;
bool stce_changed = false;
+ /* CBIE/CBCFE are read-only zero when Zicbom is not implemented. */
+ if (cfg->ext_zicbom) {
+ mask |= MENVCFG_CBIE | MENVCFG_CBCFE;
+ }
+
+ /* CBZE is read-only zero when Zicboz is not implemented. */
+ if (cfg->ext_zicboz) {
+ mask |= MENVCFG_CBZE;
+ }
+
/*
* menvcfg.LPE (Zicfilp) and menvcfg.SSE (Zicfiss) reside in the low
* 32 bits and are defined for both RV32 and RV64, so they must be
@@ -3328,8 +3337,18 @@ static RISCVException read_senvcfg(CPURISCVState *env, int csrno,
static RISCVException write_senvcfg(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
- uint64_t mask = SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCFG_CBZE;
+ uint64_t mask = SENVCFG_FIOM;
RISCVException ret;
+
+ /* CBIE/CBCFE are read-only zero when Zicbom is not implemented. */
+ if (env_archcpu(env)->cfg.ext_zicbom) {
+ mask |= SENVCFG_CBIE | SENVCFG_CBCFE;
+ }
+
+ /* CBZE is read-only zero when Zicboz is not implemented. */
+ if (env_archcpu(env)->cfg.ext_zicboz) {
+ mask |= SENVCFG_CBZE;
+ }
/* Update PMM field only if the value is valid according to Zjpm v1.0 */
if (env_archcpu(env)->cfg.ext_ssnpm &&
riscv_cpu_mxl(env) == MXL_RV64 &&
@@ -3386,10 +3405,20 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
const RISCVCPUConfig *cfg = riscv_cpu_cfg(env);
- uint64_t mask = HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCFG_CBZE;
+ uint64_t mask = HENVCFG_FIOM;
RISCVException ret;
bool stce_changed = false;
+ /* CBIE/CBCFE are read-only zero when Zicbom is not implemented. */
+ if (cfg->ext_zicbom) {
+ mask |= HENVCFG_CBIE | HENVCFG_CBCFE;
+ }
+
+ /* CBZE is read-only zero when Zicboz is not implemented. */
+ if (cfg->ext_zicboz) {
+ mask |= HENVCFG_CBZE;
+ }
+
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG);
if (ret != RISCV_EXCP_NONE) {
return ret;
--
2.43.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
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