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From: Jan Beulich <jbeulich@suse.com>
To: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Cc: "Romain Caritey" <Romain.Caritey@microchip.com>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Connor Davis" <connojdavis@gmail.com>,
	"Andrew Cooper" <andrew.cooper3@citrix.com>,
	"Anthony PERARD" <anthony.perard@vates.tech>,
	"Michal Orzel" <michal.orzel@amd.com>,
	"Julien Grall" <julien@xen.org>,
	"Roger Pau Monné" <roger.pau@citrix.com>,
	"Stefano Stabellini" <sstabellini@kernel.org>,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v7 01/14] xen/riscv: detect and store supported hypervisor CSR bits at boot
Date: Tue, 10 Mar 2026 09:17:04 +0100	[thread overview]
Message-ID: <6a4d68e3-e640-4f74-be74-132f094db752@suse.com> (raw)
In-Reply-To: <2de7f459-00b3-4968-aaa2-9067cb0c4aa4@suse.com>

On 10.03.2026 09:11, Jan Beulich wrote:
> On 06.03.2026 17:33, Oleksii Kurochko wrote:
>> +void __init init_csr_masks(void)
>> +{
>> +    /*
>> +     * The mask specifies the bits that may be safely modified without
>> +     * causing side effects.
>> +     *
>> +     * For example, registers such as henvcfg or hstateen0 contain WPRI
>> +     * fields that must be preserved. Any write to the full register must
>> +     * therefore retain the original values of those fields.
>> +     */
>> +#define INIT_CSR_MASK(csr, field, mask) do { \
>> +        register_t old = csr_read_set(CSR_##csr, mask); \
>> +        csr_masks.field = csr_swap(CSR_##csr, old); \
>> +    } while (0)
>> +
>> +#define INIT_RO_ONE_MASK(csr, field, mask) do { \
>> +        register_t old = csr_read_clear(CSR_HSTATEEN0, mask); \
>> +        csr_masks.ro_one.field = csr_swap(CSR_##csr, old) & mask; \
>> +    } while (0)
>> +
>> +    INIT_CSR_MASK(HEDELEG, hedeleg, HEDELEG_AVAIL_MASK);
>> +    INIT_CSR_MASK(HIDELEG, hideleg, HIDELEG_AVAIL_MASK);
>> +
>> +    INIT_CSR_MASK(HENVCFG, henvcfg, HENVCFG_AVAIL_MASK);
>> +
>> +    if ( riscv_isa_extension_available(NULL, RISCV_ISA_EXT_smstateen) )
>> +    {
>> +        INIT_CSR_MASK(HSTATEEN0, hstateen0, HSTATEEN0_AVAIL_MASK);
>> +        INIT_RO_ONE_MASK(HSTATEEN0, hstateen0, HSTATEEN0_AVAIL_MASK);
>> +    }
> 
> The 3rd macro parameters are now redundant. At the example of INIT_CSR_MASK(),
> you could now have
> 
> #define INIT_CSR_MASK(csr, field) do { \
>         register_t old = csr_read_set(CSR_ ## csr, csr ## _AVAIL_MASK); \
>         csr_masks.field = csr_swap(CSR_ ## csr, old); \
>     } while (0)
> 
> This would reduce the risk of incomplete editing after copy-and-paste, or
> other typo-ing.
> 
> Note also that ## being a binary operator, ./CODING_STYLE wants us to put
> blanks around it just like for non-pre-processor binary operators. I'll
> try to remember to make that adjustment when committing.

Oh, I'm also going to replace the bogus CSR_HSTATEEN0 inside the
INIT_RO_ONE_MASK() macro definition.

Jan


  reply	other threads:[~2026-03-10  8:17 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-06 16:33 [PATCH v7 00/14] xen/riscv: introduce vtimer related things Oleksii Kurochko
2026-03-06 16:33 ` [PATCH v7 01/14] xen/riscv: detect and store supported hypervisor CSR bits at boot Oleksii Kurochko
2026-03-10  8:11   ` Jan Beulich
2026-03-10  8:17     ` Jan Beulich [this message]
2026-03-10 16:00     ` Oleksii Kurochko
2026-03-10 16:14       ` Jan Beulich
2026-03-06 16:33 ` [PATCH v7 02/14] xen/riscv: implement vcpu_csr_init() Oleksii Kurochko
2026-03-06 16:33 ` [PATCH v7 03/14] xen/riscv: introduce tracking of pending vCPU interrupts, part 1 Oleksii Kurochko
2026-03-10  8:13   ` Jan Beulich
2026-03-06 16:33 ` [PATCH v7 04/14] xen/riscv: introduce tracking of pending vCPU interrupts, part 2 Oleksii Kurochko
2026-03-06 16:33 ` [PATCH v7 05/14] xen/riscv: introduce basic vtimer infrastructure for guests Oleksii Kurochko
2026-03-06 16:33 ` [PATCH v7 06/14] xen/riscv: introduce vcpu_kick() implementation Oleksii Kurochko
2026-03-06 16:33 ` [PATCH v7 07/14] xen/riscv: add vtimer context switch helpers Oleksii Kurochko
2026-03-06 16:33 ` [PATCH v7 08/14] xen/riscv: implement SBI legacy SET_TIMER support for guests Oleksii Kurochko
2026-03-06 16:33 ` [PATCH v7 09/14] xen/riscv: introduce sbi_set_timer() Oleksii Kurochko
2026-03-06 16:33 ` [PATCH v7 10/14] xen/riscv: implement reprogram_timer() via SBI Oleksii Kurochko
2026-03-06 16:33 ` [PATCH v7 11/14] xen/riscv: handle hypervisor timer interrupts Oleksii Kurochko
2026-03-06 16:33 ` [PATCH v7 12/14] xen/riscv: init tasklet subsystem Oleksii Kurochko
2026-03-06 16:33 ` [PATCH v7 13/14] xen/riscv: implement sync_vcpu_execstate() Oleksii Kurochko
2026-03-06 16:33 ` [PATCH v7 14/14] xen/riscv: Disable SSTC extension and add trap-based CSR probing Oleksii Kurochko
2026-03-10  9:15   ` Jan Beulich
2026-03-11  9:54     ` Oleksii Kurochko
2026-03-11 10:54       ` Oleksii Kurochko
2026-03-11 10:58       ` Jan Beulich
2026-03-11 11:38         ` Oleksii Kurochko
2026-03-11 12:54           ` Jan Beulich

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