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From: Christian Marangi <ansuelsmth@gmail.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Heiner Kallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	"David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@kernel.org>,
	Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
	Daniel Golle <daniel@makrotopia.org>,
	Qingfang Deng <dqfext@gmail.com>,
	SkyLake Huang <SkyLake.Huang@mediatek.com>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	Joris Vaisvila <joey@tinyisr.com>,
	Ahmed Naseef <naseefkm@gmail.com>,
	linux-kernel@vger.kernel.org, netdev@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org
Subject: Re: [PATCH net-next v4 5/6] net: phy: mediatek: add calibration logic for AN7581
Date: Wed, 4 Nov 2026 19:24:28 +0100	[thread overview]
Message-ID: <6aeb7861.6171b307.11ae12.6b94@mx.google.com> (raw)
In-Reply-To: <2b744929-609b-4529-8b6b-30feb3ebbbde@lunn.ch>

On Wed, Nov 04, 2026 at 04:47:09AM +0100, Andrew Lunn wrote:
> > +static int airoha_cal_cycle(struct phy_device *phydev, int devad,
> > +			    u32 regnum, u16 mask, u16 cal_val)
> > +{
> > +	struct airoha_socphy_shared *shared = phy_package_get_priv(phydev);
> > +	struct phy_device *phydev_p0;
> > +	int ret;
> > +
> > +	phydev_p0 = shared->phydev_p0;
> > +
> > +	phy_modify_mmd(phydev, devad, regnum, mask, cal_val);
> > +
> > +	ret = mtk_cal_cycle_wait(phydev_p0);
> > +	phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret);
> 
> What is the locking scheme here?
> 
> When using PHY packages, the typical usage is:
> 
> 	phy_lock_mdio_bus(phydev);
> 
> and then use
> 
> 	val = __phy_package_read(phydev, X, Y);
> 
> All the read/write helpers are __ indicating they assume the bus is
> locked.
> 
> Here you are doing something similar, accessing another PHY in the
> same package, but without locking. Is that safe?
> 

Hi Andrew, thanks a lot for the review tag.

It's safe in the measure that the worst is that link goes down during the
calibration... I will rework the function to assign the base address to the
default address for port 0 (it's hardcoded by the SoC) and use the lock and
read/write helper instead.

The main problem of using __phy_package_read is that I have to duplicate
the mtk_cal_cycle_wait function in the airoha-ge-soc.c as it would use
different helper... is it ok?

-- 
	Ansuel


  reply	other threads:[~2026-11-04 18:24 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-03 22:14 [PATCH net-next v4 0/6] net: phy: mediatek: calibration for AN7581/3 Christian Marangi
2026-11-03 22:14 ` [PATCH net-next v4 1/6] net: phy: mediatek: export __mtk_tr_write Christian Marangi
2026-11-04  2:32   ` Andrew Lunn
2026-11-03 22:14 ` [PATCH net-next v4 2/6] net: phy: mediatek: move MTK GE SoC registers define to dedicated header Christian Marangi
2026-11-04  2:33   ` Andrew Lunn
2026-11-03 22:14 ` [PATCH net-next v4 3/6] net: phy: mediatek: generalize cal_cycle function for GE SoC Christian Marangi
2026-11-04  2:34   ` Andrew Lunn
2026-11-03 22:14 ` [PATCH net-next v4 4/6] net: phy: mediatek: split Airoha code to dedicated source Christian Marangi
2026-11-04  2:38   ` Andrew Lunn
2026-11-03 22:14 ` [PATCH net-next v4 5/6] net: phy: mediatek: add calibration logic for AN7581 Christian Marangi
2026-11-04  3:47   ` Andrew Lunn
2026-11-04 18:24     ` Christian Marangi [this message]
2026-11-04 20:51       ` Andrew Lunn
2026-11-04 22:38         ` Benjamin Larsson
2026-11-05 22:47   ` Andrew Lunn
2026-11-06 12:09     ` Christian Marangi
2026-11-03 22:14 ` [PATCH net-next v4 6/6] net: phy: mediatek: add calibration logic for AN7583 Christian Marangi

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