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From: Marc Zyngier <maz@kernel.org>
To: Reiji Watanabe <reijiw@google.com>
Cc: kvm@vger.kernel.org, kvmarm@lists.linux.dev,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 12/16] KVM: arm64: PMU: Allow ID_DFR0_EL1.PerfMon to be set from userspace
Date: Sat, 19 Nov 2022 12:54:02 +0000	[thread overview]
Message-ID: <6b70f8fac8b2fd316b618c3c2e67e07b@kernel.org> (raw)
In-Reply-To: <CAAeT=Fwq8wcBvoWE+5RJt4og4uD5KgQ0kzhDZorGPjHmTguwzw@mail.gmail.com>

On 2022-11-19 05:52, Reiji Watanabe wrote:
> Hi Marc,
> 
> On Sun, Nov 13, 2022 at 8:46 AM Marc Zyngier <maz@kernel.org> wrote:
>> 
>> Allow userspace to write ID_DFR0_EL1, on the condition that only
>> the PerfMon field can be altered and be something that is compatible
>> with what was computed for the AArch64 view of the guest.
>> 
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>> ---
>>  arch/arm64/kvm/sys_regs.c | 57 
>> ++++++++++++++++++++++++++++++++++++++-
>>  1 file changed, 56 insertions(+), 1 deletion(-)
>> 
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index 3cbcda665d23..dc201a0557c0 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -1070,6 +1070,19 @@ static u8 vcpu_pmuver(const struct kvm_vcpu 
>> *vcpu)
>>         return vcpu->kvm->arch.dfr0_pmuver.unimp;
>>  }
>> 
>> +static u8 perfmon_to_pmuver(u8 perfmon)
>> +{
>> +       switch (perfmon) {
>> +       case ID_DFR0_PERFMON_8_0:
>> +               return ID_AA64DFR0_EL1_PMUVer_IMP;
>> +       case ID_DFR0_PERFMON_IMP_DEF:
>> +               return ID_AA64DFR0_EL1_PMUVer_IMP_DEF;
> 
> Nit: Since IMP_DEF is 0xf for both PMUVER and PERFMON,
> I think the 'default' can handle IMP_DEF (I have the same
> comment for pmuver_to_perfmon in the patch-10).

It sure can, but IMP_DEF is special enough in its treatment
(we explicitly check this value in set_id_dfr0_el1()) that
it actually helps the reader to keep the explicit conversion
here.

> 
>> +       default:
>> +               /* Anything ARMv8.1+ has the same value. For now. */
> 
> Nit: Shouldn't the comment also mention NI (and IMP_DEF) ?
> (I have the same comment for pmuver_to_perfmon in the patch-10)

I can expand the comment to include NI.

> Otherwise:
> Reviewed-by: Reiji Watanabe <reijiw@google.com>

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Reiji Watanabe <reijiw@google.com>
Cc: linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev,
	kvm@vger.kernel.org, James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Ricardo Koller <ricarkol@google.com>
Subject: Re: [PATCH v4 12/16] KVM: arm64: PMU: Allow ID_DFR0_EL1.PerfMon to be set from userspace
Date: Sat, 19 Nov 2022 12:54:02 +0000	[thread overview]
Message-ID: <6b70f8fac8b2fd316b618c3c2e67e07b@kernel.org> (raw)
Message-ID: <20221119125402.gteEG1ZHS-q1FJTxCuVYg4VkJfhH0uEgQNjDR3Vh-oc@z> (raw)
In-Reply-To: <CAAeT=Fwq8wcBvoWE+5RJt4og4uD5KgQ0kzhDZorGPjHmTguwzw@mail.gmail.com>

On 2022-11-19 05:52, Reiji Watanabe wrote:
> Hi Marc,
> 
> On Sun, Nov 13, 2022 at 8:46 AM Marc Zyngier <maz@kernel.org> wrote:
>> 
>> Allow userspace to write ID_DFR0_EL1, on the condition that only
>> the PerfMon field can be altered and be something that is compatible
>> with what was computed for the AArch64 view of the guest.
>> 
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>> ---
>>  arch/arm64/kvm/sys_regs.c | 57 
>> ++++++++++++++++++++++++++++++++++++++-
>>  1 file changed, 56 insertions(+), 1 deletion(-)
>> 
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index 3cbcda665d23..dc201a0557c0 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -1070,6 +1070,19 @@ static u8 vcpu_pmuver(const struct kvm_vcpu 
>> *vcpu)
>>         return vcpu->kvm->arch.dfr0_pmuver.unimp;
>>  }
>> 
>> +static u8 perfmon_to_pmuver(u8 perfmon)
>> +{
>> +       switch (perfmon) {
>> +       case ID_DFR0_PERFMON_8_0:
>> +               return ID_AA64DFR0_EL1_PMUVer_IMP;
>> +       case ID_DFR0_PERFMON_IMP_DEF:
>> +               return ID_AA64DFR0_EL1_PMUVer_IMP_DEF;
> 
> Nit: Since IMP_DEF is 0xf for both PMUVER and PERFMON,
> I think the 'default' can handle IMP_DEF (I have the same
> comment for pmuver_to_perfmon in the patch-10).

It sure can, but IMP_DEF is special enough in its treatment
(we explicitly check this value in set_id_dfr0_el1()) that
it actually helps the reader to keep the explicit conversion
here.

> 
>> +       default:
>> +               /* Anything ARMv8.1+ has the same value. For now. */
> 
> Nit: Shouldn't the comment also mention NI (and IMP_DEF) ?
> (I have the same comment for pmuver_to_perfmon in the patch-10)

I can expand the comment to include NI.

> Otherwise:
> Reviewed-by: Reiji Watanabe <reijiw@google.com>

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Reiji Watanabe <reijiw@google.com>
Cc: linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev,
	kvm@vger.kernel.org, James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Ricardo Koller <ricarkol@google.com>
Subject: Re: [PATCH v4 12/16] KVM: arm64: PMU: Allow ID_DFR0_EL1.PerfMon to be set from userspace
Date: Sat, 19 Nov 2022 12:54:02 +0000	[thread overview]
Message-ID: <6b70f8fac8b2fd316b618c3c2e67e07b@kernel.org> (raw)
In-Reply-To: <CAAeT=Fwq8wcBvoWE+5RJt4og4uD5KgQ0kzhDZorGPjHmTguwzw@mail.gmail.com>

On 2022-11-19 05:52, Reiji Watanabe wrote:
> Hi Marc,
> 
> On Sun, Nov 13, 2022 at 8:46 AM Marc Zyngier <maz@kernel.org> wrote:
>> 
>> Allow userspace to write ID_DFR0_EL1, on the condition that only
>> the PerfMon field can be altered and be something that is compatible
>> with what was computed for the AArch64 view of the guest.
>> 
>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>> ---
>>  arch/arm64/kvm/sys_regs.c | 57 
>> ++++++++++++++++++++++++++++++++++++++-
>>  1 file changed, 56 insertions(+), 1 deletion(-)
>> 
>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
>> index 3cbcda665d23..dc201a0557c0 100644
>> --- a/arch/arm64/kvm/sys_regs.c
>> +++ b/arch/arm64/kvm/sys_regs.c
>> @@ -1070,6 +1070,19 @@ static u8 vcpu_pmuver(const struct kvm_vcpu 
>> *vcpu)
>>         return vcpu->kvm->arch.dfr0_pmuver.unimp;
>>  }
>> 
>> +static u8 perfmon_to_pmuver(u8 perfmon)
>> +{
>> +       switch (perfmon) {
>> +       case ID_DFR0_PERFMON_8_0:
>> +               return ID_AA64DFR0_EL1_PMUVer_IMP;
>> +       case ID_DFR0_PERFMON_IMP_DEF:
>> +               return ID_AA64DFR0_EL1_PMUVer_IMP_DEF;
> 
> Nit: Since IMP_DEF is 0xf for both PMUVER and PERFMON,
> I think the 'default' can handle IMP_DEF (I have the same
> comment for pmuver_to_perfmon in the patch-10).

It sure can, but IMP_DEF is special enough in its treatment
(we explicitly check this value in set_id_dfr0_el1()) that
it actually helps the reader to keep the explicit conversion
here.

> 
>> +       default:
>> +               /* Anything ARMv8.1+ has the same value. For now. */
> 
> Nit: Shouldn't the comment also mention NI (and IMP_DEF) ?
> (I have the same comment for pmuver_to_perfmon in the patch-10)

I can expand the comment to include NI.

> Otherwise:
> Reviewed-by: Reiji Watanabe <reijiw@google.com>

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2022-11-19 12:54 UTC|newest]

Thread overview: 111+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-13 16:38 [PATCH v4 00/16] KVM: arm64: PMU: Fixing chained events, and PMUv3p5 support Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-13 16:38 ` Marc Zyngier
2022-11-13 16:38 ` [PATCH v4 01/16] arm64: Add ID_DFR0_EL1.PerfMon values for PMUv3p7 and IMP_DEF Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38 ` [PATCH v4 02/16] KVM: arm64: PMU: Align chained counter implementation with architecture pseudocode Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-16  7:15   ` Reiji Watanabe
2022-11-16  7:15     ` Reiji Watanabe
2022-11-16  7:15     ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 03/16] KVM: arm64: PMU: Always advertise the CHAIN event Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38 ` [PATCH v4 04/16] KVM: arm64: PMU: Distinguish between 64bit counter and 64bit overflow Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-12-01 16:47   ` Ricardo Koller
2022-12-01 16:47     ` Ricardo Koller
2022-12-01 16:47     ` Ricardo Koller
2022-12-01 16:51     ` Ricardo Koller
2022-12-01 16:51       ` Ricardo Koller
2022-12-01 16:51       ` Ricardo Koller
2022-12-05 12:05       ` Marc Zyngier
2022-12-05 12:05         ` Marc Zyngier
2022-12-05 12:05         ` Marc Zyngier
2022-12-05 18:50         ` Ricardo Koller
2022-12-05 18:50           ` Ricardo Koller
2022-12-05 18:50           ` Ricardo Koller
2022-11-13 16:38 ` [PATCH v4 05/16] KVM: arm64: PMU: Narrow the overflow checking when required Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-17  6:50   ` Reiji Watanabe
2022-11-17  6:50     ` Reiji Watanabe
2022-11-17  6:50     ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 06/16] KVM: arm64: PMU: Only narrow counters that are not 64bit wide Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-17  6:54   ` Reiji Watanabe
2022-11-17  6:54     ` Reiji Watanabe
2022-11-17  6:54     ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 07/16] KVM: arm64: PMU: Add counter_index_to_*reg() helpers Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-18  6:16   ` Reiji Watanabe
2022-11-18  6:16     ` Reiji Watanabe
2022-11-18  6:16     ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 08/16] KVM: arm64: PMU: Simplify setting a counter to a specific value Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38 ` [PATCH v4 09/16] KVM: arm64: PMU: Do not let AArch32 change the counters' top 32 bits Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-18  7:45   ` Reiji Watanabe
2022-11-18  7:45     ` Reiji Watanabe
2022-11-18  7:45     ` Reiji Watanabe
2022-11-19 12:32     ` Marc Zyngier
2022-11-19 12:32       ` Marc Zyngier
2022-11-19 12:32       ` Marc Zyngier
2022-11-13 16:38 ` [PATCH v4 10/16] KVM: arm64: PMU: Move the ID_AA64DFR0_EL1.PMUver limit to VM creation Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38 ` [PATCH v4 11/16] KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-19  5:31   ` Reiji Watanabe
2022-11-19  5:31     ` Reiji Watanabe
2022-11-19  5:31     ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 12/16] KVM: arm64: PMU: Allow ID_DFR0_EL1.PerfMon " Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-19  5:52   ` Reiji Watanabe
2022-11-19  5:52     ` Reiji Watanabe
2022-11-19  5:52     ` Reiji Watanabe
2022-11-19 12:54     ` Marc Zyngier [this message]
2022-11-19 12:54       ` Marc Zyngier
2022-11-19 12:54       ` Marc Zyngier
2022-11-13 16:38 ` [PATCH v4 13/16] KVM: arm64: PMU: Implement PMUv3p5 long counter support Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-23  5:58   ` Reiji Watanabe
2022-11-23  5:58     ` Reiji Watanabe
2022-11-23  5:58     ` Reiji Watanabe
2022-11-23 11:11     ` Marc Zyngier
2022-11-23 11:11       ` Marc Zyngier
2022-11-23 11:11       ` Marc Zyngier
2022-11-23 17:11       ` Reiji Watanabe
2022-11-23 17:11         ` Reiji Watanabe
2022-11-23 17:11         ` Reiji Watanabe
2022-11-24 10:17         ` Marc Zyngier
2022-11-24 10:17           ` Marc Zyngier
2022-11-24 10:17           ` Marc Zyngier
2022-11-29  3:03           ` Reiji Watanabe
2022-11-29  3:03             ` Reiji Watanabe
2022-11-29  3:03             ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 14/16] KVM: arm64: PMU: Allow PMUv3p5 to be exposed to the guest Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-23  6:07   ` Reiji Watanabe
2022-11-23  6:07     ` Reiji Watanabe
2022-11-23  6:07     ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 15/16] KVM: arm64: PMU: Simplify vcpu computation on perf overflow notification Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-23  6:27   ` Reiji Watanabe
2022-11-23  6:27     ` Reiji Watanabe
2022-11-23  6:27     ` Reiji Watanabe
2022-11-13 16:38 ` [PATCH v4 16/16] KVM: arm64: PMU: Make kvm_pmc the main data structure Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier
2022-11-13 16:38   ` Marc Zyngier

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