From: Chris Wilson <chris@chris-wilson.co.uk>
To: Paulo Zanoni <przanoni@gmail.com>, intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH 3/3] drm/i915: fix FDI lane calculation
Date: Thu, 29 Nov 2012 13:59:55 +0000 [thread overview]
Message-ID: <6c3329$7dllih@orsmga002.jf.intel.com> (raw)
In-Reply-To: <1354195773-4022-3-git-send-email-przanoni@gmail.com>
On Thu, 29 Nov 2012 11:29:33 -0200, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> The previous code was making the bps value 5% higher than what the
> spec says, which was enough to make certain VGA modes require 3 lanes
> instead of 2, which makes us reject these modes on Haswell since it
> only has 2 FDI lanes. For previous gens this was not much of a
> problem, since they had 4 lanes, and requiring more lanes than the
> needed is ok, as long as you have all the lanes.
>
> Notice that this might improve the case where we use pipes B and C on
> Ivy Bridge since both pipes only have 4 lanes to share (see
> ironlake_check_fdi_lanes).
>
> Cc: Adam Jackson <ajax@redhat.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> As it is, this one will make the list of supported modes on Haswell VGA bigger,
> so we could skip 3.8 and send this through 3.9, so we have plently of time to
> get confident this won't break older platforms.
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 8d86a39..1825ae7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5231,12 +5231,10 @@ static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
> int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
> {
> /*
> - * Account for spread spectrum to avoid
> - * oversubscribing the link. Max center spread
> - * is 2.5%; use 5% for safety's sake.
> + * The spec says:
> + * Number of lanes >= INT(dot clock * bytes per pixel / ls_clk)
> */
> - u32 bps = target_clock * bpp * 21 / 20;
> - return bps / (link_bw * 8) + 1;
> + return DIV_ROUND_UP(target_clock * bpp, link_bw * 8);
Can you split this into two patches, one for using DIV_ROUND_UP and for
removingthe oversubscription, as the DIV_ROUND_UP looks to be a separate
issue worth testing. (Handling the case where bps % (link_bw * 8) == 0.)
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-11-29 14:00 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-11-29 13:29 [PATCH 1/3] drm/i915: fix hsw_fdi_link_train "retry" code Paulo Zanoni
2012-11-29 13:29 ` [PATCH 2/3] drm/i915: reject modes the LPT FDI receiver can't handle Paulo Zanoni
2012-12-08 13:00 ` Daniel Vetter
2012-11-29 13:29 ` [PATCH 3/3] drm/i915: fix FDI lane calculation Paulo Zanoni
2012-11-29 13:59 ` Chris Wilson [this message]
2012-11-29 16:16 ` Adam Jackson
2012-11-29 21:54 ` [PATCH 1/3] drm/i915: fix hsw_fdi_link_train "retry" code Daniel Vetter
2012-11-30 15:39 ` Paulo Zanoni
2012-11-30 15:46 ` Daniel Vetter
2012-12-08 12:59 ` Daniel Vetter
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