[igt-dev] [PATCH i-g-t 1/3] benchmarks/gem_syslatency: Pass a write hazard around

[igt-dev] [PATCH i-g-t 1/3] benchmarks/gem_syslatency: Pass a write hazard around

[Chris Wilson]

Extend the i915 load to (optionally) pass a write hazard between
engines, causing us to wait on the interrupt between engines. Thus
adding MI_USER_INTERRUPT irq handling to our list of sins.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 benchmarks/gem_syslatency.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
index de59eaf82..9160e2199 100644
--- a/benchmarks/gem_syslatency.c
+++ b/benchmarks/gem_syslatency.c
@@ -53,6 +53,7 @@ struct gem_busyspin {
 	pthread_t thread;
 	unsigned long count;
 	bool leak;
+	bool interrupts;
 };
 
 struct sys_wait {
@@ -94,7 +95,7 @@ static void *gem_busyspin(void *arg)
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	struct gem_busyspin *bs = arg;
 	struct drm_i915_gem_execbuffer2 execbuf;
-	struct drm_i915_gem_exec_object2 obj;
+	struct drm_i915_gem_exec_object2 obj[2];
 	const unsigned sz = bs->leak ? 16 << 20 : 4 << 10;
 	unsigned engines[16];
 	unsigned nengine;
@@ -107,13 +108,15 @@ static void *gem_busyspin(void *arg)
 	for_each_engine(fd, engine)
 		if (!ignore_engine(fd, engine)) engines[nengine++] = engine;
 
-	memset(&obj, 0, sizeof(obj));
-	obj.handle = gem_create(fd, sz);
-	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
+	memset(obj, 0, sizeof(obj));
+	obj[0].handle = gem_create(fd, 4096);
+	obj[0].flags = EXEC_OBJECT_WRITE;
+	obj[1].handle = gem_create(fd, sz);
+	gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
 
 	memset(&execbuf, 0, sizeof(execbuf));
-	execbuf.buffers_ptr = (uintptr_t)&obj;
-	execbuf.buffer_count = 1;
+	execbuf.buffers_ptr = (uintptr_t)(obj + !bs->interrupts);
+	execbuf.buffer_count = 1 + !!bs->interrupts;
 	execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
 	execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
 	if (__gem_execbuf(fd, &execbuf)) {
@@ -129,9 +132,9 @@ static void *gem_busyspin(void *arg)
 		}
 		bs->count += nengine;
 		if (bs->leak) {
-			gem_madvise(fd, obj.handle, I915_MADV_DONTNEED);
-			obj.handle = gem_create(fd, sz);
-			gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
+			gem_madvise(fd, obj[1].handle, I915_MADV_DONTNEED);
+			obj[1].handle = gem_create(fd, sz);
+			gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
 		}
 	}
 
@@ -305,13 +308,17 @@ int main(int argc, char **argv)
 	int field = -1;
 	int enable_gem_sysbusy = 1;
 	bool leak = false;
+	bool interrupts = false;
 	int n, c;
 
-	while ((c = getopt(argc, argv, "t:f:bmn")) != -1) {
+	while ((c = getopt(argc, argv, "t:f:bmni")) != -1) {
 		switch (c) {
 		case 'n': /* dry run, measure baseline system latency */
 			enable_gem_sysbusy = 0;
 			break;
+		case 'i': /* interrupts ahoy! */
+			interrupts = true;
+			break;
 		case 't':
 			/* How long to run the benchmark for (seconds) */
 			time = atoi(optarg);
@@ -346,6 +353,7 @@ int main(int argc, char **argv)
 		for (n = 0; n < ncpus; n++) {
 			bind_cpu(&attr, n);
 			busy[n].leak = leak;
+			busy[n].interrupts = interrupts;
 			pthread_create(&busy[n].thread, &attr,
 				       gem_busyspin, &busy[n]);
 		}
-- 
2.17.0

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[PATCH i-g-t 1/3] benchmarks/gem_syslatency: Pass a write hazard around

[Chris Wilson]

Extend the i915 load to (optionally) pass a write hazard between
engines, causing us to wait on the interrupt between engines. Thus
adding MI_USER_INTERRUPT irq handling to our list of sins.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 benchmarks/gem_syslatency.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
index de59eaf82..9160e2199 100644
--- a/benchmarks/gem_syslatency.c
+++ b/benchmarks/gem_syslatency.c
@@ -53,6 +53,7 @@ struct gem_busyspin {
 	pthread_t thread;
 	unsigned long count;
 	bool leak;
+	bool interrupts;
 };
 
 struct sys_wait {
@@ -94,7 +95,7 @@ static void *gem_busyspin(void *arg)
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	struct gem_busyspin *bs = arg;
 	struct drm_i915_gem_execbuffer2 execbuf;
-	struct drm_i915_gem_exec_object2 obj;
+	struct drm_i915_gem_exec_object2 obj[2];
 	const unsigned sz = bs->leak ? 16 << 20 : 4 << 10;
 	unsigned engines[16];
 	unsigned nengine;
@@ -107,13 +108,15 @@ static void *gem_busyspin(void *arg)
 	for_each_engine(fd, engine)
 		if (!ignore_engine(fd, engine)) engines[nengine++] = engine;
 
-	memset(&obj, 0, sizeof(obj));
-	obj.handle = gem_create(fd, sz);
-	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
+	memset(obj, 0, sizeof(obj));
+	obj[0].handle = gem_create(fd, 4096);
+	obj[0].flags = EXEC_OBJECT_WRITE;
+	obj[1].handle = gem_create(fd, sz);
+	gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
 
 	memset(&execbuf, 0, sizeof(execbuf));
-	execbuf.buffers_ptr = (uintptr_t)&obj;
-	execbuf.buffer_count = 1;
+	execbuf.buffers_ptr = (uintptr_t)(obj + !bs->interrupts);
+	execbuf.buffer_count = 1 + !!bs->interrupts;
 	execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
 	execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
 	if (__gem_execbuf(fd, &execbuf)) {
@@ -129,9 +132,9 @@ static void *gem_busyspin(void *arg)
 		}
 		bs->count += nengine;
 		if (bs->leak) {
-			gem_madvise(fd, obj.handle, I915_MADV_DONTNEED);
-			obj.handle = gem_create(fd, sz);
-			gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
+			gem_madvise(fd, obj[1].handle, I915_MADV_DONTNEED);
+			obj[1].handle = gem_create(fd, sz);
+			gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
 		}
 	}
 
@@ -305,13 +308,17 @@ int main(int argc, char **argv)
 	int field = -1;
 	int enable_gem_sysbusy = 1;
 	bool leak = false;
+	bool interrupts = false;
 	int n, c;
 
-	while ((c = getopt(argc, argv, "t:f:bmn")) != -1) {
+	while ((c = getopt(argc, argv, "t:f:bmni")) != -1) {
 		switch (c) {
 		case 'n': /* dry run, measure baseline system latency */
 			enable_gem_sysbusy = 0;
 			break;
+		case 'i': /* interrupts ahoy! */
+			interrupts = true;
+			break;
 		case 't':
 			/* How long to run the benchmark for (seconds) */
 			time = atoi(optarg);
@@ -346,6 +353,7 @@ int main(int argc, char **argv)
 		for (n = 0; n < ncpus; n++) {
 			bind_cpu(&attr, n);
 			busy[n].leak = leak;
+			busy[n].interrupts = interrupts;
 			pthread_create(&busy[n].thread, &attr,
 				       gem_busyspin, &busy[n]);
 		}
-- 
2.17.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH i-g-t 2/3] benchmarks/gem_syslatency: Allow limiting to just 1 CPU hog

[Chris Wilson]

Normally we use a hog per CPU to ensure that the system is fully
loaded to see how much latency we cause. For simple sanitychecking, allow
ourselves to limit it to just one CPU hog.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 benchmarks/gem_syslatency.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
index 9160e2199..d1056773a 100644
--- a/benchmarks/gem_syslatency.c
+++ b/benchmarks/gem_syslatency.c
@@ -311,8 +311,11 @@ int main(int argc, char **argv)
 	bool interrupts = false;
 	int n, c;
 
-	while ((c = getopt(argc, argv, "t:f:bmni")) != -1) {
+	while ((c = getopt(argc, argv, "t:f:bmni1")) != -1) {
 		switch (c) {
+		case '1':
+			ncpus = 1;
+			break;
 		case 'n': /* dry run, measure baseline system latency */
 			enable_gem_sysbusy = 0;
 			break;
-- 
2.17.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH i-g-t 2/3] benchmarks/gem_syslatency: Allow limiting to just 1 CPU hog

[Chris Wilson]

Normally we use a hog per CPU to ensure that the system is fully
loaded to see how much latency we cause. For simple sanitychecking, allow
ourselves to limit it to just one CPU hog.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 benchmarks/gem_syslatency.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
index 9160e2199..d1056773a 100644
--- a/benchmarks/gem_syslatency.c
+++ b/benchmarks/gem_syslatency.c
@@ -311,8 +311,11 @@ int main(int argc, char **argv)
 	bool interrupts = false;
 	int n, c;
 
-	while ((c = getopt(argc, argv, "t:f:bmni")) != -1) {
+	while ((c = getopt(argc, argv, "t:f:bmni1")) != -1) {
 		switch (c) {
+		case '1':
+			ncpus = 1;
+			break;
 		case 'n': /* dry run, measure baseline system latency */
 			enable_gem_sysbusy = 0;
 			break;
-- 
2.17.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[igt-dev] [PATCH i-g-t 3/3] benchmarks/gem_syslatency: Specify batch duration

[Chris Wilson]

While for stressing the system we want to submit as many batches as we
can as that shows us worst case impact on system latency, it is not a
very realistic case. To introduce a bit more realism allow the batches
run for a user defined duration.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 benchmarks/gem_syslatency.c | 71 ++++++++++++++++++++++++++++++++++---
 1 file changed, 67 insertions(+), 4 deletions(-)

diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
index d1056773a..45cabe86c 100644
--- a/benchmarks/gem_syslatency.c
+++ b/benchmarks/gem_syslatency.c
@@ -51,6 +51,7 @@ static volatile int done;
 
 struct gem_busyspin {
 	pthread_t thread;
+	unsigned long sz;
 	unsigned long count;
 	bool leak;
 	bool interrupts;
@@ -96,7 +97,8 @@ static void *gem_busyspin(void *arg)
 	struct gem_busyspin *bs = arg;
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 obj[2];
-	const unsigned sz = bs->leak ? 16 << 20 : 4 << 10;
+	const unsigned sz =
+		bs->sz ? bs->sz + sizeof(bbe) : bs->leak ? 16 << 20 : 4 << 10;
 	unsigned engines[16];
 	unsigned nengine;
 	unsigned engine;
@@ -112,7 +114,7 @@ static void *gem_busyspin(void *arg)
 	obj[0].handle = gem_create(fd, 4096);
 	obj[0].flags = EXEC_OBJECT_WRITE;
 	obj[1].handle = gem_create(fd, sz);
-	gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
+	gem_write(fd, obj[1].handle, bs->sz, &bbe, sizeof(bbe));
 
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = (uintptr_t)(obj + !bs->interrupts);
@@ -125,6 +127,12 @@ static void *gem_busyspin(void *arg)
 	}
 
 	while (!done) {
+		for (int n = 0; n < nengine; n++) {
+			const int m = rand() % nengine;
+			unsigned int tmp = engines[n];
+			engines[n] = engines[m];
+			engines[m] = tmp;
+		}
 		for (int n = 0; n < nengine; n++) {
 			execbuf.flags &= ~ENGINE_FLAGS;
 			execbuf.flags |= engines[n];
@@ -134,7 +142,7 @@ static void *gem_busyspin(void *arg)
 		if (bs->leak) {
 			gem_madvise(fd, obj[1].handle, I915_MADV_DONTNEED);
 			obj[1].handle = gem_create(fd, sz);
-			gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
+			gem_write(fd, obj[1].handle, bs->sz, &bbe, sizeof(bbe));
 		}
 	}
 
@@ -294,6 +302,50 @@ static void *background_fs(void *path)
 	return NULL;
 }
 
+static unsigned long calibrate_nop(unsigned int target_us,
+				   unsigned int tolerance_pct)
+{
+	const uint32_t bbe = MI_BATCH_BUFFER_END;
+	const unsigned int loops = 100;
+	struct drm_i915_gem_exec_object2 obj = {};
+	struct drm_i915_gem_execbuffer2 eb =
+		{ .buffer_count = 1, .buffers_ptr = (uintptr_t)&obj};
+	struct timespec t_0, t_end;
+	long sz, prev;
+	int fd;
+
+	fd = drm_open_driver(DRIVER_INTEL);
+
+	clock_gettime(CLOCK_MONOTONIC, &t_0);
+
+	sz = 256 * 1024;
+	do {
+		struct timespec t_start;
+
+		obj.handle = gem_create(fd, sz + sizeof(bbe));
+		gem_write(fd, obj.handle, sz, &bbe, sizeof(bbe));
+		gem_execbuf(fd, &eb);
+		gem_sync(fd, obj.handle);
+
+		clock_gettime(CLOCK_MONOTONIC, &t_start);
+		for (int loop = 0; loop < loops; loop++)
+			gem_execbuf(fd, &eb);
+		gem_sync(fd, obj.handle);
+		clock_gettime(CLOCK_MONOTONIC, &t_end);
+
+		gem_close(fd, obj.handle);
+
+		prev = sz;
+		sz = loops * sz / elapsed(&t_start, &t_end) * 1e3 * target_us;
+		sz = ALIGN(sz, sizeof(uint32_t));
+	} while (elapsed(&t_0, &t_end) < 5 ||
+		 abs(sz - prev) > (sz * tolerance_pct / 100));
+
+	close(fd);
+
+	return sz;
+}
+
 int main(int argc, char **argv)
 {
 	struct gem_busyspin *busy;
@@ -309,9 +361,10 @@ int main(int argc, char **argv)
 	int enable_gem_sysbusy = 1;
 	bool leak = false;
 	bool interrupts = false;
+	long batch = 0;
 	int n, c;
 
-	while ((c = getopt(argc, argv, "t:f:bmni1")) != -1) {
+	while ((c = getopt(argc, argv, "r:t:f:bmni1")) != -1) {
 		switch (c) {
 		case '1':
 			ncpus = 1;
@@ -328,6 +381,10 @@ int main(int argc, char **argv)
 			if (time < 0)
 				time = INT_MAX;
 			break;
+		case 'r':
+			/* Duration of each batch (microseconds) */
+			batch = atoi(optarg);
+			break;
 		case 'f':
 			/* Select an output field */
 			field = atoi(optarg);
@@ -350,11 +407,17 @@ int main(int argc, char **argv)
 	force_low_latency();
 	min = min_measurement_error();
 
+	if (batch > 0)
+		batch = calibrate_nop(batch, 2);
+	else
+		batch = -batch;
+
 	busy = calloc(ncpus, sizeof(*busy));
 	pthread_attr_init(&attr);
 	if (enable_gem_sysbusy) {
 		for (n = 0; n < ncpus; n++) {
 			bind_cpu(&attr, n);
+			busy[n].sz = batch;
 			busy[n].leak = leak;
 			busy[n].interrupts = interrupts;
 			pthread_create(&busy[n].thread, &attr,
-- 
2.17.0

_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[PATCH i-g-t 3/3] benchmarks/gem_syslatency: Specify batch duration

[Chris Wilson]

While for stressing the system we want to submit as many batches as we
can as that shows us worst case impact on system latency, it is not a
very realistic case. To introduce a bit more realism allow the batches
run for a user defined duration.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 benchmarks/gem_syslatency.c | 71 ++++++++++++++++++++++++++++++++++---
 1 file changed, 67 insertions(+), 4 deletions(-)

diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
index d1056773a..45cabe86c 100644
--- a/benchmarks/gem_syslatency.c
+++ b/benchmarks/gem_syslatency.c
@@ -51,6 +51,7 @@ static volatile int done;
 
 struct gem_busyspin {
 	pthread_t thread;
+	unsigned long sz;
 	unsigned long count;
 	bool leak;
 	bool interrupts;
@@ -96,7 +97,8 @@ static void *gem_busyspin(void *arg)
 	struct gem_busyspin *bs = arg;
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 obj[2];
-	const unsigned sz = bs->leak ? 16 << 20 : 4 << 10;
+	const unsigned sz =
+		bs->sz ? bs->sz + sizeof(bbe) : bs->leak ? 16 << 20 : 4 << 10;
 	unsigned engines[16];
 	unsigned nengine;
 	unsigned engine;
@@ -112,7 +114,7 @@ static void *gem_busyspin(void *arg)
 	obj[0].handle = gem_create(fd, 4096);
 	obj[0].flags = EXEC_OBJECT_WRITE;
 	obj[1].handle = gem_create(fd, sz);
-	gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
+	gem_write(fd, obj[1].handle, bs->sz, &bbe, sizeof(bbe));
 
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = (uintptr_t)(obj + !bs->interrupts);
@@ -125,6 +127,12 @@ static void *gem_busyspin(void *arg)
 	}
 
 	while (!done) {
+		for (int n = 0; n < nengine; n++) {
+			const int m = rand() % nengine;
+			unsigned int tmp = engines[n];
+			engines[n] = engines[m];
+			engines[m] = tmp;
+		}
 		for (int n = 0; n < nengine; n++) {
 			execbuf.flags &= ~ENGINE_FLAGS;
 			execbuf.flags |= engines[n];
@@ -134,7 +142,7 @@ static void *gem_busyspin(void *arg)
 		if (bs->leak) {
 			gem_madvise(fd, obj[1].handle, I915_MADV_DONTNEED);
 			obj[1].handle = gem_create(fd, sz);
-			gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
+			gem_write(fd, obj[1].handle, bs->sz, &bbe, sizeof(bbe));
 		}
 	}
 
@@ -294,6 +302,50 @@ static void *background_fs(void *path)
 	return NULL;
 }
 
+static unsigned long calibrate_nop(unsigned int target_us,
+				   unsigned int tolerance_pct)
+{
+	const uint32_t bbe = MI_BATCH_BUFFER_END;
+	const unsigned int loops = 100;
+	struct drm_i915_gem_exec_object2 obj = {};
+	struct drm_i915_gem_execbuffer2 eb =
+		{ .buffer_count = 1, .buffers_ptr = (uintptr_t)&obj};
+	struct timespec t_0, t_end;
+	long sz, prev;
+	int fd;
+
+	fd = drm_open_driver(DRIVER_INTEL);
+
+	clock_gettime(CLOCK_MONOTONIC, &t_0);
+
+	sz = 256 * 1024;
+	do {
+		struct timespec t_start;
+
+		obj.handle = gem_create(fd, sz + sizeof(bbe));
+		gem_write(fd, obj.handle, sz, &bbe, sizeof(bbe));
+		gem_execbuf(fd, &eb);
+		gem_sync(fd, obj.handle);
+
+		clock_gettime(CLOCK_MONOTONIC, &t_start);
+		for (int loop = 0; loop < loops; loop++)
+			gem_execbuf(fd, &eb);
+		gem_sync(fd, obj.handle);
+		clock_gettime(CLOCK_MONOTONIC, &t_end);
+
+		gem_close(fd, obj.handle);
+
+		prev = sz;
+		sz = loops * sz / elapsed(&t_start, &t_end) * 1e3 * target_us;
+		sz = ALIGN(sz, sizeof(uint32_t));
+	} while (elapsed(&t_0, &t_end) < 5 ||
+		 abs(sz - prev) > (sz * tolerance_pct / 100));
+
+	close(fd);
+
+	return sz;
+}
+
 int main(int argc, char **argv)
 {
 	struct gem_busyspin *busy;
@@ -309,9 +361,10 @@ int main(int argc, char **argv)
 	int enable_gem_sysbusy = 1;
 	bool leak = false;
 	bool interrupts = false;
+	long batch = 0;
 	int n, c;
 
-	while ((c = getopt(argc, argv, "t:f:bmni1")) != -1) {
+	while ((c = getopt(argc, argv, "r:t:f:bmni1")) != -1) {
 		switch (c) {
 		case '1':
 			ncpus = 1;
@@ -328,6 +381,10 @@ int main(int argc, char **argv)
 			if (time < 0)
 				time = INT_MAX;
 			break;
+		case 'r':
+			/* Duration of each batch (microseconds) */
+			batch = atoi(optarg);
+			break;
 		case 'f':
 			/* Select an output field */
 			field = atoi(optarg);
@@ -350,11 +407,17 @@ int main(int argc, char **argv)
 	force_low_latency();
 	min = min_measurement_error();
 
+	if (batch > 0)
+		batch = calibrate_nop(batch, 2);
+	else
+		batch = -batch;
+
 	busy = calloc(ncpus, sizeof(*busy));
 	pthread_attr_init(&attr);
 	if (enable_gem_sysbusy) {
 		for (n = 0; n < ncpus; n++) {
 			bind_cpu(&attr, n);
+			busy[n].sz = batch;
 			busy[n].leak = leak;
 			busy[n].interrupts = interrupts;
 			pthread_create(&busy[n].thread, &attr,
-- 
2.17.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 1/3] benchmarks/gem_syslatency: Pass a write hazard around

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Extend the i915 load to (optionally) pass a write hazard between
> engines, causing us to wait on the interrupt between engines. Thus
> adding MI_USER_INTERRUPT irq handling to our list of sins.


Is it the eb_move_to_gpu waiting then for the object
due to write?

..and this then arming the interrupts later down the
chain?

-Mika

>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  benchmarks/gem_syslatency.c | 28 ++++++++++++++++++----------
>  1 file changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
> index de59eaf82..9160e2199 100644
> --- a/benchmarks/gem_syslatency.c
> +++ b/benchmarks/gem_syslatency.c
> @@ -53,6 +53,7 @@ struct gem_busyspin {
>  	pthread_t thread;
>  	unsigned long count;
>  	bool leak;
> +	bool interrupts;
>  };
>  
>  struct sys_wait {
> @@ -94,7 +95,7 @@ static void *gem_busyspin(void *arg)
>  	const uint32_t bbe = MI_BATCH_BUFFER_END;
>  	struct gem_busyspin *bs = arg;
>  	struct drm_i915_gem_execbuffer2 execbuf;
> -	struct drm_i915_gem_exec_object2 obj;
> +	struct drm_i915_gem_exec_object2 obj[2];
>  	const unsigned sz = bs->leak ? 16 << 20 : 4 << 10;
>  	unsigned engines[16];
>  	unsigned nengine;
> @@ -107,13 +108,15 @@ static void *gem_busyspin(void *arg)
>  	for_each_engine(fd, engine)
>  		if (!ignore_engine(fd, engine)) engines[nengine++] = engine;
>  
> -	memset(&obj, 0, sizeof(obj));
> -	obj.handle = gem_create(fd, sz);
> -	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> +	memset(obj, 0, sizeof(obj));
> +	obj[0].handle = gem_create(fd, 4096);
> +	obj[0].flags = EXEC_OBJECT_WRITE;
> +	obj[1].handle = gem_create(fd, sz);
> +	gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
>  
>  	memset(&execbuf, 0, sizeof(execbuf));
> -	execbuf.buffers_ptr = (uintptr_t)&obj;
> -	execbuf.buffer_count = 1;
> +	execbuf.buffers_ptr = (uintptr_t)(obj + !bs->interrupts);
> +	execbuf.buffer_count = 1 + !!bs->interrupts;
>  	execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
>  	execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
>  	if (__gem_execbuf(fd, &execbuf)) {
> @@ -129,9 +132,9 @@ static void *gem_busyspin(void *arg)
>  		}
>  		bs->count += nengine;
>  		if (bs->leak) {
> -			gem_madvise(fd, obj.handle, I915_MADV_DONTNEED);
> -			obj.handle = gem_create(fd, sz);
> -			gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> +			gem_madvise(fd, obj[1].handle, I915_MADV_DONTNEED);
> +			obj[1].handle = gem_create(fd, sz);
> +			gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
>  		}
>  	}
>  
> @@ -305,13 +308,17 @@ int main(int argc, char **argv)
>  	int field = -1;
>  	int enable_gem_sysbusy = 1;
>  	bool leak = false;
> +	bool interrupts = false;
>  	int n, c;
>  
> -	while ((c = getopt(argc, argv, "t:f:bmn")) != -1) {
> +	while ((c = getopt(argc, argv, "t:f:bmni")) != -1) {
>  		switch (c) {
>  		case 'n': /* dry run, measure baseline system latency */
>  			enable_gem_sysbusy = 0;
>  			break;
> +		case 'i': /* interrupts ahoy! */
> +			interrupts = true;
> +			break;
>  		case 't':
>  			/* How long to run the benchmark for (seconds) */
>  			time = atoi(optarg);
> @@ -346,6 +353,7 @@ int main(int argc, char **argv)
>  		for (n = 0; n < ncpus; n++) {
>  			bind_cpu(&attr, n);
>  			busy[n].leak = leak;
> +			busy[n].interrupts = interrupts;
>  			pthread_create(&busy[n].thread, &attr,
>  				       gem_busyspin, &busy[n]);
>  		}
> -- 
> 2.17.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [PATCH i-g-t 1/3] benchmarks/gem_syslatency: Pass a write hazard around

[Mika Kuoppala]

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Extend the i915 load to (optionally) pass a write hazard between
> engines, causing us to wait on the interrupt between engines. Thus
> adding MI_USER_INTERRUPT irq handling to our list of sins.


Is it the eb_move_to_gpu waiting then for the object
due to write?

..and this then arming the interrupts later down the
chain?

-Mika

>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>  benchmarks/gem_syslatency.c | 28 ++++++++++++++++++----------
>  1 file changed, 18 insertions(+), 10 deletions(-)
>
> diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
> index de59eaf82..9160e2199 100644
> --- a/benchmarks/gem_syslatency.c
> +++ b/benchmarks/gem_syslatency.c
> @@ -53,6 +53,7 @@ struct gem_busyspin {
>  	pthread_t thread;
>  	unsigned long count;
>  	bool leak;
> +	bool interrupts;
>  };
>  
>  struct sys_wait {
> @@ -94,7 +95,7 @@ static void *gem_busyspin(void *arg)
>  	const uint32_t bbe = MI_BATCH_BUFFER_END;
>  	struct gem_busyspin *bs = arg;
>  	struct drm_i915_gem_execbuffer2 execbuf;
> -	struct drm_i915_gem_exec_object2 obj;
> +	struct drm_i915_gem_exec_object2 obj[2];
>  	const unsigned sz = bs->leak ? 16 << 20 : 4 << 10;
>  	unsigned engines[16];
>  	unsigned nengine;
> @@ -107,13 +108,15 @@ static void *gem_busyspin(void *arg)
>  	for_each_engine(fd, engine)
>  		if (!ignore_engine(fd, engine)) engines[nengine++] = engine;
>  
> -	memset(&obj, 0, sizeof(obj));
> -	obj.handle = gem_create(fd, sz);
> -	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> +	memset(obj, 0, sizeof(obj));
> +	obj[0].handle = gem_create(fd, 4096);
> +	obj[0].flags = EXEC_OBJECT_WRITE;
> +	obj[1].handle = gem_create(fd, sz);
> +	gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
>  
>  	memset(&execbuf, 0, sizeof(execbuf));
> -	execbuf.buffers_ptr = (uintptr_t)&obj;
> -	execbuf.buffer_count = 1;
> +	execbuf.buffers_ptr = (uintptr_t)(obj + !bs->interrupts);
> +	execbuf.buffer_count = 1 + !!bs->interrupts;
>  	execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
>  	execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
>  	if (__gem_execbuf(fd, &execbuf)) {
> @@ -129,9 +132,9 @@ static void *gem_busyspin(void *arg)
>  		}
>  		bs->count += nengine;
>  		if (bs->leak) {
> -			gem_madvise(fd, obj.handle, I915_MADV_DONTNEED);
> -			obj.handle = gem_create(fd, sz);
> -			gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> +			gem_madvise(fd, obj[1].handle, I915_MADV_DONTNEED);
> +			obj[1].handle = gem_create(fd, sz);
> +			gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
>  		}
>  	}
>  
> @@ -305,13 +308,17 @@ int main(int argc, char **argv)
>  	int field = -1;
>  	int enable_gem_sysbusy = 1;
>  	bool leak = false;
> +	bool interrupts = false;
>  	int n, c;
>  
> -	while ((c = getopt(argc, argv, "t:f:bmn")) != -1) {
> +	while ((c = getopt(argc, argv, "t:f:bmni")) != -1) {
>  		switch (c) {
>  		case 'n': /* dry run, measure baseline system latency */
>  			enable_gem_sysbusy = 0;
>  			break;
> +		case 'i': /* interrupts ahoy! */
> +			interrupts = true;
> +			break;
>  		case 't':
>  			/* How long to run the benchmark for (seconds) */
>  			time = atoi(optarg);
> @@ -346,6 +353,7 @@ int main(int argc, char **argv)
>  		for (n = 0; n < ncpus; n++) {
>  			bind_cpu(&attr, n);
>  			busy[n].leak = leak;
> +			busy[n].interrupts = interrupts;
>  			pthread_create(&busy[n].thread, &attr,
>  				       gem_busyspin, &busy[n]);
>  		}
> -- 
> 2.17.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 1/3] benchmarks/gem_syslatency: Pass a write hazard around

[Chris Wilson]

Quoting Mika Kuoppala (2018-05-22 12:24:59)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > Extend the i915 load to (optionally) pass a write hazard between
> > engines, causing us to wait on the interrupt between engines. Thus
> > adding MI_USER_INTERRUPT irq handling to our list of sins.
> 
> 
> Is it the eb_move_to_gpu waiting then for the object
> due to write?

Don't be silly! That was like 3 years ago :-p
 
> ..and this then arming the interrupts later down the
> chain?

i915_gem_request_await_object adds the callback for the request to be
submitted when its dependencies are complete.
-Chris
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [PATCH i-g-t 1/3] benchmarks/gem_syslatency: Pass a write hazard around

[Chris Wilson]

Quoting Mika Kuoppala (2018-05-22 12:24:59)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> 
> > Extend the i915 load to (optionally) pass a write hazard between
> > engines, causing us to wait on the interrupt between engines. Thus
> > adding MI_USER_INTERRUPT irq handling to our list of sins.
> 
> 
> Is it the eb_move_to_gpu waiting then for the object
> due to write?

Don't be silly! That was like 3 years ago :-p
 
> ..and this then arming the interrupts later down the
> chain?

i915_gem_request_await_object adds the callback for the request to be
submitted when its dependencies are complete.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 1/3] benchmarks/gem_syslatency: Pass a write hazard around

[Tvrtko Ursulin]

On 22/05/2018 12:00, Chris Wilson wrote:
> Extend the i915 load to (optionally) pass a write hazard between
> engines, causing us to wait on the interrupt between engines. Thus
> adding MI_USER_INTERRUPT irq handling to our list of sins.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   benchmarks/gem_syslatency.c | 28 ++++++++++++++++++----------
>   1 file changed, 18 insertions(+), 10 deletions(-)
> 
> diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
> index de59eaf82..9160e2199 100644
> --- a/benchmarks/gem_syslatency.c
> +++ b/benchmarks/gem_syslatency.c
> @@ -53,6 +53,7 @@ struct gem_busyspin {
>   	pthread_t thread;
>   	unsigned long count;
>   	bool leak;
> +	bool interrupts;
>   };
>   
>   struct sys_wait {
> @@ -94,7 +95,7 @@ static void *gem_busyspin(void *arg)
>   	const uint32_t bbe = MI_BATCH_BUFFER_END;
>   	struct gem_busyspin *bs = arg;
>   	struct drm_i915_gem_execbuffer2 execbuf;
> -	struct drm_i915_gem_exec_object2 obj;
> +	struct drm_i915_gem_exec_object2 obj[2];
>   	const unsigned sz = bs->leak ? 16 << 20 : 4 << 10;
>   	unsigned engines[16];
>   	unsigned nengine;
> @@ -107,13 +108,15 @@ static void *gem_busyspin(void *arg)
>   	for_each_engine(fd, engine)
>   		if (!ignore_engine(fd, engine)) engines[nengine++] = engine;
>   
> -	memset(&obj, 0, sizeof(obj));
> -	obj.handle = gem_create(fd, sz);
> -	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> +	memset(obj, 0, sizeof(obj));
> +	obj[0].handle = gem_create(fd, 4096);
> +	obj[0].flags = EXEC_OBJECT_WRITE;
> +	obj[1].handle = gem_create(fd, sz);
> +	gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
>   
>   	memset(&execbuf, 0, sizeof(execbuf));
> -	execbuf.buffers_ptr = (uintptr_t)&obj;
> -	execbuf.buffer_count = 1;
> +	execbuf.buffers_ptr = (uintptr_t)(obj + !bs->interrupts);
> +	execbuf.buffer_count = 1 + !!bs->interrupts;

Above two lines are to hacky. :/ Suggest a more pedestrian approach with 
a ternary or something.

>   	execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
>   	execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
>   	if (__gem_execbuf(fd, &execbuf)) {
> @@ -129,9 +132,9 @@ static void *gem_busyspin(void *arg)
>   		}
>   		bs->count += nengine;
>   		if (bs->leak) {
> -			gem_madvise(fd, obj.handle, I915_MADV_DONTNEED);
> -			obj.handle = gem_create(fd, sz);
> -			gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> +			gem_madvise(fd, obj[1].handle, I915_MADV_DONTNEED);
> +			obj[1].handle = gem_create(fd, sz);
> +			gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
>   		}
>   	}
>   
> @@ -305,13 +308,17 @@ int main(int argc, char **argv)
>   	int field = -1;
>   	int enable_gem_sysbusy = 1;
>   	bool leak = false;
> +	bool interrupts = false;
>   	int n, c;
>   
> -	while ((c = getopt(argc, argv, "t:f:bmn")) != -1) {
> +	while ((c = getopt(argc, argv, "t:f:bmni")) != -1) {
>   		switch (c) {
>   		case 'n': /* dry run, measure baseline system latency */
>   			enable_gem_sysbusy = 0;
>   			break;
> +		case 'i': /* interrupts ahoy! */
> +			interrupts = true;
> +			break;
>   		case 't':
>   			/* How long to run the benchmark for (seconds) */
>   			time = atoi(optarg);
> @@ -346,6 +353,7 @@ int main(int argc, char **argv)
>   		for (n = 0; n < ncpus; n++) {
>   			bind_cpu(&attr, n);
>   			busy[n].leak = leak;
> +			busy[n].interrupts = interrupts;
>   			pthread_create(&busy[n].thread, &attr,
>   				       gem_busyspin, &busy[n]);
>   		}
> 

With the hackery eliminated:

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [PATCH i-g-t 1/3] benchmarks/gem_syslatency: Pass a write hazard around

[Tvrtko Ursulin]

On 22/05/2018 12:00, Chris Wilson wrote:
> Extend the i915 load to (optionally) pass a write hazard between
> engines, causing us to wait on the interrupt between engines. Thus
> adding MI_USER_INTERRUPT irq handling to our list of sins.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   benchmarks/gem_syslatency.c | 28 ++++++++++++++++++----------
>   1 file changed, 18 insertions(+), 10 deletions(-)
> 
> diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
> index de59eaf82..9160e2199 100644
> --- a/benchmarks/gem_syslatency.c
> +++ b/benchmarks/gem_syslatency.c
> @@ -53,6 +53,7 @@ struct gem_busyspin {
>   	pthread_t thread;
>   	unsigned long count;
>   	bool leak;
> +	bool interrupts;
>   };
>   
>   struct sys_wait {
> @@ -94,7 +95,7 @@ static void *gem_busyspin(void *arg)
>   	const uint32_t bbe = MI_BATCH_BUFFER_END;
>   	struct gem_busyspin *bs = arg;
>   	struct drm_i915_gem_execbuffer2 execbuf;
> -	struct drm_i915_gem_exec_object2 obj;
> +	struct drm_i915_gem_exec_object2 obj[2];
>   	const unsigned sz = bs->leak ? 16 << 20 : 4 << 10;
>   	unsigned engines[16];
>   	unsigned nengine;
> @@ -107,13 +108,15 @@ static void *gem_busyspin(void *arg)
>   	for_each_engine(fd, engine)
>   		if (!ignore_engine(fd, engine)) engines[nengine++] = engine;
>   
> -	memset(&obj, 0, sizeof(obj));
> -	obj.handle = gem_create(fd, sz);
> -	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> +	memset(obj, 0, sizeof(obj));
> +	obj[0].handle = gem_create(fd, 4096);
> +	obj[0].flags = EXEC_OBJECT_WRITE;
> +	obj[1].handle = gem_create(fd, sz);
> +	gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
>   
>   	memset(&execbuf, 0, sizeof(execbuf));
> -	execbuf.buffers_ptr = (uintptr_t)&obj;
> -	execbuf.buffer_count = 1;
> +	execbuf.buffers_ptr = (uintptr_t)(obj + !bs->interrupts);
> +	execbuf.buffer_count = 1 + !!bs->interrupts;

Above two lines are to hacky. :/ Suggest a more pedestrian approach with 
a ternary or something.

>   	execbuf.flags |= LOCAL_I915_EXEC_HANDLE_LUT;
>   	execbuf.flags |= LOCAL_I915_EXEC_NO_RELOC;
>   	if (__gem_execbuf(fd, &execbuf)) {
> @@ -129,9 +132,9 @@ static void *gem_busyspin(void *arg)
>   		}
>   		bs->count += nengine;
>   		if (bs->leak) {
> -			gem_madvise(fd, obj.handle, I915_MADV_DONTNEED);
> -			obj.handle = gem_create(fd, sz);
> -			gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> +			gem_madvise(fd, obj[1].handle, I915_MADV_DONTNEED);
> +			obj[1].handle = gem_create(fd, sz);
> +			gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
>   		}
>   	}
>   
> @@ -305,13 +308,17 @@ int main(int argc, char **argv)
>   	int field = -1;
>   	int enable_gem_sysbusy = 1;
>   	bool leak = false;
> +	bool interrupts = false;
>   	int n, c;
>   
> -	while ((c = getopt(argc, argv, "t:f:bmn")) != -1) {
> +	while ((c = getopt(argc, argv, "t:f:bmni")) != -1) {
>   		switch (c) {
>   		case 'n': /* dry run, measure baseline system latency */
>   			enable_gem_sysbusy = 0;
>   			break;
> +		case 'i': /* interrupts ahoy! */
> +			interrupts = true;
> +			break;
>   		case 't':
>   			/* How long to run the benchmark for (seconds) */
>   			time = atoi(optarg);
> @@ -346,6 +353,7 @@ int main(int argc, char **argv)
>   		for (n = 0; n < ncpus; n++) {
>   			bind_cpu(&attr, n);
>   			busy[n].leak = leak;
> +			busy[n].interrupts = interrupts;
>   			pthread_create(&busy[n].thread, &attr,
>   				       gem_busyspin, &busy[n]);
>   		}
> 

With the hackery eliminated:

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [igt-dev] [Intel-gfx] [PATCH i-g-t 2/3] benchmarks/gem_syslatency: Allow limiting to just 1 CPU hog

[Tvrtko Ursulin]

On 22/05/2018 12:00, Chris Wilson wrote:
> Normally we use a hog per CPU to ensure that the system is fully
> loaded to see how much latency we cause. For simple sanitychecking, allow
> ourselves to limit it to just one CPU hog.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   benchmarks/gem_syslatency.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
> index 9160e2199..d1056773a 100644
> --- a/benchmarks/gem_syslatency.c
> +++ b/benchmarks/gem_syslatency.c
> @@ -311,8 +311,11 @@ int main(int argc, char **argv)
>   	bool interrupts = false;
>   	int n, c;
>   
> -	while ((c = getopt(argc, argv, "t:f:bmni")) != -1) {
> +	while ((c = getopt(argc, argv, "t:f:bmni1")) != -1) {
>   		switch (c) {
> +		case '1':
> +			ncpus = 1;
> +			break;
>   		case 'n': /* dry run, measure baseline system latency */
>   			enable_gem_sysbusy = 0;
>   			break;
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Re: [PATCH i-g-t 2/3] benchmarks/gem_syslatency: Allow limiting to just 1 CPU hog

[Tvrtko Ursulin]

On 22/05/2018 12:00, Chris Wilson wrote:
> Normally we use a hog per CPU to ensure that the system is fully
> loaded to see how much latency we cause. For simple sanitychecking, allow
> ourselves to limit it to just one CPU hog.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   benchmarks/gem_syslatency.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
> index 9160e2199..d1056773a 100644
> --- a/benchmarks/gem_syslatency.c
> +++ b/benchmarks/gem_syslatency.c
> @@ -311,8 +311,11 @@ int main(int argc, char **argv)
>   	bool interrupts = false;
>   	int n, c;
>   
> -	while ((c = getopt(argc, argv, "t:f:bmni")) != -1) {
> +	while ((c = getopt(argc, argv, "t:f:bmni1")) != -1) {
>   		switch (c) {
> +		case '1':
> +			ncpus = 1;
> +			break;
>   		case 'n': /* dry run, measure baseline system latency */
>   			enable_gem_sysbusy = 0;
>   			break;
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH i-g-t 3/3] benchmarks/gem_syslatency: Specify batch duration

[Tvrtko Ursulin]

On 22/05/2018 12:00, Chris Wilson wrote:
> While for stressing the system we want to submit as many batches as we
> can as that shows us worst case impact on system latency, it is not a
> very realistic case. To introduce a bit more realism allow the batches
> run for a user defined duration.
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   benchmarks/gem_syslatency.c | 71 ++++++++++++++++++++++++++++++++++---
>   1 file changed, 67 insertions(+), 4 deletions(-)
> 
> diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
> index d1056773a..45cabe86c 100644
> --- a/benchmarks/gem_syslatency.c
> +++ b/benchmarks/gem_syslatency.c
> @@ -51,6 +51,7 @@ static volatile int done;
>   
>   struct gem_busyspin {
>   	pthread_t thread;
> +	unsigned long sz;
>   	unsigned long count;
>   	bool leak;
>   	bool interrupts;
> @@ -96,7 +97,8 @@ static void *gem_busyspin(void *arg)
>   	struct gem_busyspin *bs = arg;
>   	struct drm_i915_gem_execbuffer2 execbuf;
>   	struct drm_i915_gem_exec_object2 obj[2];
> -	const unsigned sz = bs->leak ? 16 << 20 : 4 << 10;
> +	const unsigned sz =
> +		bs->sz ? bs->sz + sizeof(bbe) : bs->leak ? 16 << 20 : 4 << 10;
>   	unsigned engines[16];
>   	unsigned nengine;
>   	unsigned engine;
> @@ -112,7 +114,7 @@ static void *gem_busyspin(void *arg)
>   	obj[0].handle = gem_create(fd, 4096);
>   	obj[0].flags = EXEC_OBJECT_WRITE;
>   	obj[1].handle = gem_create(fd, sz);
> -	gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
> +	gem_write(fd, obj[1].handle, bs->sz, &bbe, sizeof(bbe));

Hm what was the point in creating large batches here if bbend was always 
first?

>   
>   	memset(&execbuf, 0, sizeof(execbuf));
>   	execbuf.buffers_ptr = (uintptr_t)(obj + !bs->interrupts);
> @@ -125,6 +127,12 @@ static void *gem_busyspin(void *arg)
>   	}
>   
>   	while (!done) {
> +		for (int n = 0; n < nengine; n++) {
> +			const int m = rand() % nengine;
> +			unsigned int tmp = engines[n];
> +			engines[n] = engines[m];
> +			engines[m] = tmp;

igt_exchange_int? Problem with frameworks getting more featureful is 
easier to forget what is there. :) Or even igt_permute_array?

But what it has to do with batch duration?

> +		}
>   		for (int n = 0; n < nengine; n++) {
>   			execbuf.flags &= ~ENGINE_FLAGS;
>   			execbuf.flags |= engines[n];
> @@ -134,7 +142,7 @@ static void *gem_busyspin(void *arg)
>   		if (bs->leak) {
>   			gem_madvise(fd, obj[1].handle, I915_MADV_DONTNEED);
>   			obj[1].handle = gem_create(fd, sz);
> -			gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
> +			gem_write(fd, obj[1].handle, bs->sz, &bbe, sizeof(bbe));
>   		}
>   	}
>   
> @@ -294,6 +302,50 @@ static void *background_fs(void *path)
>   	return NULL;
>   }
>   
> +static unsigned long calibrate_nop(unsigned int target_us,
> +				   unsigned int tolerance_pct)
> +{
> +	const uint32_t bbe = MI_BATCH_BUFFER_END;
> +	const unsigned int loops = 100;
> +	struct drm_i915_gem_exec_object2 obj = {};
> +	struct drm_i915_gem_execbuffer2 eb =
> +		{ .buffer_count = 1, .buffers_ptr = (uintptr_t)&obj};
> +	struct timespec t_0, t_end;
> +	long sz, prev;
> +	int fd;
> +
> +	fd = drm_open_driver(DRIVER_INTEL);
> +
> +	clock_gettime(CLOCK_MONOTONIC, &t_0);
> +
> +	sz = 256 * 1024;
> +	do {
> +		struct timespec t_start;
> +
> +		obj.handle = gem_create(fd, sz + sizeof(bbe));
> +		gem_write(fd, obj.handle, sz, &bbe, sizeof(bbe));
> +		gem_execbuf(fd, &eb);
> +		gem_sync(fd, obj.handle);
> +
> +		clock_gettime(CLOCK_MONOTONIC, &t_start);
> +		for (int loop = 0; loop < loops; loop++)
> +			gem_execbuf(fd, &eb);
> +		gem_sync(fd, obj.handle);
> +		clock_gettime(CLOCK_MONOTONIC, &t_end);
> +
> +		gem_close(fd, obj.handle);
> +
> +		prev = sz;
> +		sz = loops * sz / elapsed(&t_start, &t_end) * 1e3 * target_us;
> +		sz = ALIGN(sz, sizeof(uint32_t));
> +	} while (elapsed(&t_0, &t_end) < 5 ||
> +		 abs(sz - prev) > (sz * tolerance_pct / 100));
> +
> +	close(fd);
> +
> +	return sz;
> +}

I presume this is a copy&paste so don't have to look into it in detail.

> +
>   int main(int argc, char **argv)
>   {
>   	struct gem_busyspin *busy;
> @@ -309,9 +361,10 @@ int main(int argc, char **argv)
>   	int enable_gem_sysbusy = 1;
>   	bool leak = false;
>   	bool interrupts = false;
> +	long batch = 0;
>   	int n, c;
>   
> -	while ((c = getopt(argc, argv, "t:f:bmni1")) != -1) {
> +	while ((c = getopt(argc, argv, "r:t:f:bmni1")) != -1) {
>   		switch (c) {
>   		case '1':
>   			ncpus = 1;
> @@ -328,6 +381,10 @@ int main(int argc, char **argv)
>   			if (time < 0)
>   				time = INT_MAX;
>   			break;
> +		case 'r':
> +			/* Duration of each batch (microseconds) */
> +			batch = atoi(optarg);
> +			break;
>   		case 'f':
>   			/* Select an output field */
>   			field = atoi(optarg);
> @@ -350,11 +407,17 @@ int main(int argc, char **argv)
>   	force_low_latency();
>   	min = min_measurement_error();
>   
> +	if (batch > 0)
> +		batch = calibrate_nop(batch, 2);
> +	else
> +		batch = -batch;
> +

No idea of the purpose of this. User passes in negative on the cmd line? 
But then calibration is missing.

>   	busy = calloc(ncpus, sizeof(*busy));
>   	pthread_attr_init(&attr);
>   	if (enable_gem_sysbusy) {
>   		for (n = 0; n < ncpus; n++) {
>   			bind_cpu(&attr, n);
> +			busy[n].sz = batch;
>   			busy[n].leak = leak;
>   			busy[n].interrupts = interrupts;
>   			pthread_create(&busy[n].thread, &attr,
> 

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH i-g-t 3/3] benchmarks/gem_syslatency: Specify batch duration

[Tvrtko Ursulin]

On 22/05/2018 12:00, Chris Wilson wrote:
> While for stressing the system we want to submit as many batches as we
> can as that shows us worst case impact on system latency, it is not a
> very realistic case. To introduce a bit more realism allow the batches
> run for a user defined duration.
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   benchmarks/gem_syslatency.c | 71 ++++++++++++++++++++++++++++++++++---
>   1 file changed, 67 insertions(+), 4 deletions(-)
> 
> diff --git a/benchmarks/gem_syslatency.c b/benchmarks/gem_syslatency.c
> index d1056773a..45cabe86c 100644
> --- a/benchmarks/gem_syslatency.c
> +++ b/benchmarks/gem_syslatency.c
> @@ -51,6 +51,7 @@ static volatile int done;
>   
>   struct gem_busyspin {
>   	pthread_t thread;
> +	unsigned long sz;
>   	unsigned long count;
>   	bool leak;
>   	bool interrupts;
> @@ -96,7 +97,8 @@ static void *gem_busyspin(void *arg)
>   	struct gem_busyspin *bs = arg;
>   	struct drm_i915_gem_execbuffer2 execbuf;
>   	struct drm_i915_gem_exec_object2 obj[2];
> -	const unsigned sz = bs->leak ? 16 << 20 : 4 << 10;
> +	const unsigned sz =
> +		bs->sz ? bs->sz + sizeof(bbe) : bs->leak ? 16 << 20 : 4 << 10;
>   	unsigned engines[16];
>   	unsigned nengine;
>   	unsigned engine;
> @@ -112,7 +114,7 @@ static void *gem_busyspin(void *arg)
>   	obj[0].handle = gem_create(fd, 4096);
>   	obj[0].flags = EXEC_OBJECT_WRITE;
>   	obj[1].handle = gem_create(fd, sz);
> -	gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
> +	gem_write(fd, obj[1].handle, bs->sz, &bbe, sizeof(bbe));

Hm what was the point in creating large batches here if bbend was always 
first?

>   
>   	memset(&execbuf, 0, sizeof(execbuf));
>   	execbuf.buffers_ptr = (uintptr_t)(obj + !bs->interrupts);
> @@ -125,6 +127,12 @@ static void *gem_busyspin(void *arg)
>   	}
>   
>   	while (!done) {
> +		for (int n = 0; n < nengine; n++) {
> +			const int m = rand() % nengine;
> +			unsigned int tmp = engines[n];
> +			engines[n] = engines[m];
> +			engines[m] = tmp;

igt_exchange_int? Problem with frameworks getting more featureful is 
easier to forget what is there. :) Or even igt_permute_array?

But what it has to do with batch duration?

> +		}
>   		for (int n = 0; n < nengine; n++) {
>   			execbuf.flags &= ~ENGINE_FLAGS;
>   			execbuf.flags |= engines[n];
> @@ -134,7 +142,7 @@ static void *gem_busyspin(void *arg)
>   		if (bs->leak) {
>   			gem_madvise(fd, obj[1].handle, I915_MADV_DONTNEED);
>   			obj[1].handle = gem_create(fd, sz);
> -			gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe));
> +			gem_write(fd, obj[1].handle, bs->sz, &bbe, sizeof(bbe));
>   		}
>   	}
>   
> @@ -294,6 +302,50 @@ static void *background_fs(void *path)
>   	return NULL;
>   }
>   
> +static unsigned long calibrate_nop(unsigned int target_us,
> +				   unsigned int tolerance_pct)
> +{
> +	const uint32_t bbe = MI_BATCH_BUFFER_END;
> +	const unsigned int loops = 100;
> +	struct drm_i915_gem_exec_object2 obj = {};
> +	struct drm_i915_gem_execbuffer2 eb =
> +		{ .buffer_count = 1, .buffers_ptr = (uintptr_t)&obj};
> +	struct timespec t_0, t_end;
> +	long sz, prev;
> +	int fd;
> +
> +	fd = drm_open_driver(DRIVER_INTEL);
> +
> +	clock_gettime(CLOCK_MONOTONIC, &t_0);
> +
> +	sz = 256 * 1024;
> +	do {
> +		struct timespec t_start;
> +
> +		obj.handle = gem_create(fd, sz + sizeof(bbe));
> +		gem_write(fd, obj.handle, sz, &bbe, sizeof(bbe));
> +		gem_execbuf(fd, &eb);
> +		gem_sync(fd, obj.handle);
> +
> +		clock_gettime(CLOCK_MONOTONIC, &t_start);
> +		for (int loop = 0; loop < loops; loop++)
> +			gem_execbuf(fd, &eb);
> +		gem_sync(fd, obj.handle);
> +		clock_gettime(CLOCK_MONOTONIC, &t_end);
> +
> +		gem_close(fd, obj.handle);
> +
> +		prev = sz;
> +		sz = loops * sz / elapsed(&t_start, &t_end) * 1e3 * target_us;
> +		sz = ALIGN(sz, sizeof(uint32_t));
> +	} while (elapsed(&t_0, &t_end) < 5 ||
> +		 abs(sz - prev) > (sz * tolerance_pct / 100));
> +
> +	close(fd);
> +
> +	return sz;
> +}

I presume this is a copy&paste so don't have to look into it in detail.

> +
>   int main(int argc, char **argv)
>   {
>   	struct gem_busyspin *busy;
> @@ -309,9 +361,10 @@ int main(int argc, char **argv)
>   	int enable_gem_sysbusy = 1;
>   	bool leak = false;
>   	bool interrupts = false;
> +	long batch = 0;
>   	int n, c;
>   
> -	while ((c = getopt(argc, argv, "t:f:bmni1")) != -1) {
> +	while ((c = getopt(argc, argv, "r:t:f:bmni1")) != -1) {
>   		switch (c) {
>   		case '1':
>   			ncpus = 1;
> @@ -328,6 +381,10 @@ int main(int argc, char **argv)
>   			if (time < 0)
>   				time = INT_MAX;
>   			break;
> +		case 'r':
> +			/* Duration of each batch (microseconds) */
> +			batch = atoi(optarg);
> +			break;
>   		case 'f':
>   			/* Select an output field */
>   			field = atoi(optarg);
> @@ -350,11 +407,17 @@ int main(int argc, char **argv)
>   	force_low_latency();
>   	min = min_measurement_error();
>   
> +	if (batch > 0)
> +		batch = calibrate_nop(batch, 2);
> +	else
> +		batch = -batch;
> +

No idea of the purpose of this. User passes in negative on the cmd line? 
But then calibration is missing.

>   	busy = calloc(ncpus, sizeof(*busy));
>   	pthread_attr_init(&attr);
>   	if (enable_gem_sysbusy) {
>   		for (n = 0; n < ncpus; n++) {
>   			bind_cpu(&attr, n);
> +			busy[n].sz = batch;
>   			busy[n].leak = leak;
>   			busy[n].interrupts = interrupts;
>   			pthread_create(&busy[n].thread, &attr,
> 

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/3] benchmarks/gem_syslatency: Pass a write hazard around

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,1/3] benchmarks/gem_syslatency: Pass a write hazard around
URL   : https://patchwork.freedesktop.org/series/43567/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4218 -> IGTPW_1383 =

== Summary - WARNING ==

  Minor unknown changes coming with IGTPW_1383 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_1383, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/43567/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in IGTPW_1383:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_gttfill@basic:
      fi-pnv-d510:        SKIP -> PASS

    
== Known issues ==

  Here are the changes found in IGTPW_1383 that come from known issues:

  === IGT changes ===

    ==== Possible fixes ====

    igt@kms_flip@basic-flip-vs-wf_vblank:
      fi-cnl-psr:         FAIL (fdo#100368) -> PASS

    igt@kms_frontbuffer_tracking@basic:
      fi-hsw-peppy:       DMESG-FAIL (fdo#102614, fdo#106103) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
  fdo#106103 https://bugs.freedesktop.org/show_bug.cgi?id=106103


== Participating hosts (44 -> 39) ==

  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-skl-6700hq 


== Build changes ==

    * IGT: IGT_4489 -> IGTPW_1383
    * Piglit: piglit_4489 -> piglit_4490

  CI_DRM_4218: df2fa6a1766287fc138a6088c48c306191edaf01 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1383: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1383/
  IGT_4489: d8d5dde407e7f7b17850be71d24a7e679533b03d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4489: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit
  piglit_4490: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1383/issues.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev

[igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,1/3] benchmarks/gem_syslatency: Pass a write hazard around

[Patchwork]

== Series Details ==

Series: series starting with [i-g-t,1/3] benchmarks/gem_syslatency: Pass a write hazard around
URL   : https://patchwork.freedesktop.org/series/43567/
State : success

== Summary ==

= CI Bug Log - changes from IGT_4489_full -> IGTPW_1383_full =

== Summary - WARNING ==

  Minor unknown changes coming with IGTPW_1383_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_1383_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/43567/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in IGTPW_1383_full:

  === IGT changes ===

    ==== Possible regressions ====

    {igt@kms_available_modes_crc@available_mode_test_crc}:
      shard-apl:          NOTRUN -> FAIL
      shard-glk:          NOTRUN -> FAIL
      shard-hsw:          NOTRUN -> FAIL
      shard-kbl:          NOTRUN -> FAIL

    
    ==== Warnings ====

    igt@gem_mocs_settings@mocs-rc6-dirty-render:
      shard-kbl:          PASS -> SKIP +1

    igt@pm_rc6_residency@rc6-accuracy:
      shard-snb:          PASS -> SKIP

    
== Known issues ==

  Here are the changes found in IGTPW_1383_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_suspend@fence-restore-tiled2untiled:
      shard-snb:          PASS -> INCOMPLETE (fdo#105411)
      shard-hsw:          PASS -> INCOMPLETE (fdo#103540)

    igt@gem_exec_suspend@basic-s3-devices:
      shard-kbl:          PASS -> DMESG-WARN (fdo#104238)

    igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic:
      shard-glk:          PASS -> FAIL (fdo#106509, fdo#105454)

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-glk:          PASS -> FAIL (fdo#102887)

    igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
      shard-snb:          PASS -> FAIL (fdo#104724, fdo#103166)

    igt@kms_setmode@basic:
      shard-glk:          PASS -> FAIL (fdo#99912)

    igt@kms_vblank@pipe-c-query-busy:
      shard-apl:          PASS -> DMESG-WARN (fdo#105602, fdo#103558) +10

    igt@perf_pmu@busy-accuracy-50-rcs0:
      shard-glk:          PASS -> FAIL (fdo#105157)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      shard-kbl:          DMESG-FAIL (fdo#106560) -> PASS

    igt@drv_suspend@sysfs-reader:
      shard-hsw:          INCOMPLETE (fdo#103540) -> PASS
      shard-apl:          INCOMPLETE (fdo#103927) -> PASS
      shard-snb:          INCOMPLETE (fdo#105411) -> PASS
      shard-kbl:          INCOMPLETE (fdo#103665) -> PASS

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
      shard-glk:          FAIL (fdo#105703) -> PASS +1

    igt@kms_flip@2x-blocking-wf_vblank:
      shard-glk:          INCOMPLETE (fdo#103359, k.org#198133) -> PASS +1

    igt@kms_flip@flip-vs-expired-vblank:
      shard-hsw:          FAIL (fdo#105707) -> PASS

    igt@kms_flip@plain-flip-fb-recreate-interruptible:
      shard-hsw:          FAIL (fdo#100368) -> PASS

    igt@kms_flip_tiling@flip-to-x-tiled:
      shard-glk:          FAIL (fdo#104724, fdo#103822) -> PASS

    igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-pwrite:
      shard-glk:          DMESG-WARN (fdo#106247) -> PASS

    igt@kms_rotation_crc@sprite-rotation-180:
      shard-snb:          FAIL (fdo#104724, fdo#103925) -> PASS +1

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104238 https://bugs.freedesktop.org/show_bug.cgi?id=104238
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105157 https://bugs.freedesktop.org/show_bug.cgi?id=105157
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#105707 https://bugs.freedesktop.org/show_bug.cgi?id=105707
  fdo#106247 https://bugs.freedesktop.org/show_bug.cgi?id=106247
  fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (9 -> 5) ==

  Missing    (4): pig-snb-2600 pig-glk-j5005 pig-skl-6600 pig-hsw-4770r 


== Build changes ==

    * IGT: IGT_4489 -> IGTPW_1383
    * Linux: CI_DRM_4212 -> CI_DRM_4218
    * Piglit: piglit_4489 -> piglit_4490

  CI_DRM_4212: da383fb02111a4871806a3a31c4a5996243829a5 @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_4218: df2fa6a1766287fc138a6088c48c306191edaf01 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1383: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1383/
  IGT_4489: d8d5dde407e7f7b17850be71d24a7e679533b03d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  piglit_4489: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit
  piglit_4490: 6ab75f7eb5e1dccbb773e1739beeb2d7cbd6ad0d @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1383/shards.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev