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From: Matthias Brugger <matthias.bgg@gmail.com>
To: Zhi Mao <zhi.mao@mediatek.com>
Cc: john@phrozen.org, Thierry Reding <thierry.reding@gmail.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	linux-pwm@vger.kernel.org, srv_heupstream@mediatek.com,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org, yingjoe.chen@mediatek.com,
	yt.shen@mediatek.com, sean.wang@mediatek.com,
	zhenbao.liu@mediatek.com
Subject: Re: [PATCH v3 2/6] pwm: mediatek: fix pwm source clock selection
Date: Tue, 18 Jul 2017 18:34:17 +0200	[thread overview]
Message-ID: <6d74d623-e08d-3552-8d4e-b109d06589c5@gmail.com> (raw)
In-Reply-To: <1499323435.22478.26.camel@mhfsdcap03>



On 07/06/2017 08:43 AM, Zhi Mao wrote:
> On Thu, 2017-07-06 at 14:16 +0800, Zhi Mao wrote:
>> On Wed, 2017-07-05 at 13:09 +0200, Matthias Brugger wrote:
>>>
>>> On 06/30/2017 08:05 AM, Zhi Mao wrote:
>>>> In original code, the pwm output frequency is not correct
>>>> when set bit<3>=1 to PWMCON register.
>>>>
>>>> Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
>>>> ---
>>>>    drivers/pwm/pwm-mediatek.c |    2 +-
>>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
>>>> index 5c11bc7..d08b5b3 100644
>>>> --- a/drivers/pwm/pwm-mediatek.c
>>>> +++ b/drivers/pwm/pwm-mediatek.c
>>>> @@ -91,7 +91,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
>>>>    	if (clkdiv > 7)
>>>>    		return -EINVAL;
>>>>    
>>>> -	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
>>>> +	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
>>>
>>> Just for clarification, BIT(15) enables old PWM mode, which ignores
>>> CLKSEL (BIT(3)). Therefore setting BIT(3) does not have any effect and
>>> can be discarded.
>>>
>>> Am I correct? I took mt7623n datasheet for reference.
>>>
>>> Regards,
>>> Matthias
>>>
>> Yes, remove setting bit<3> will not take any effect.
>> PWMCON bit<3> is pwm source clock selecting register.
>> You can check the datasheet of MT7623 for details.
>>
>> Regards
>> Zhi
>>
> Hi Mattias,
> 
> Ignore the above reply, I explain this bit<3> issue for you.
> In the data sheet of MT7623:
> PWMCON bit<3> is PWM source clock selecting register
> 0: CLK=CLKSRC
> 1: CLK=CLKSRC/1625
> for example,
> bit<3>=0, PWM clk source is 26M
> bit<3>=1, PWM clk source is 16K
> The frequency of PWM output will based on this clock source
> if set bit<3>=1, it will cause the frequency of PWM output is not
> correct. I also use the oscilloscope device to measure the output,
> set bit<3>=0, the output meet expectation.
>   

Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

WARNING: multiple messages have this Message-ID (diff)
From: matthias.bgg@gmail.com (Matthias Brugger)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/6] pwm: mediatek: fix pwm source clock selection
Date: Tue, 18 Jul 2017 18:34:17 +0200	[thread overview]
Message-ID: <6d74d623-e08d-3552-8d4e-b109d06589c5@gmail.com> (raw)
In-Reply-To: <1499323435.22478.26.camel@mhfsdcap03>



On 07/06/2017 08:43 AM, Zhi Mao wrote:
> On Thu, 2017-07-06 at 14:16 +0800, Zhi Mao wrote:
>> On Wed, 2017-07-05 at 13:09 +0200, Matthias Brugger wrote:
>>>
>>> On 06/30/2017 08:05 AM, Zhi Mao wrote:
>>>> In original code, the pwm output frequency is not correct
>>>> when set bit<3>=1 to PWMCON register.
>>>>
>>>> Signed-off-by: Zhi Mao <zhi.mao@mediatek.com>
>>>> ---
>>>>    drivers/pwm/pwm-mediatek.c |    2 +-
>>>>    1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c
>>>> index 5c11bc7..d08b5b3 100644
>>>> --- a/drivers/pwm/pwm-mediatek.c
>>>> +++ b/drivers/pwm/pwm-mediatek.c
>>>> @@ -91,7 +91,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
>>>>    	if (clkdiv > 7)
>>>>    		return -EINVAL;
>>>>    
>>>> -	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | BIT(3) | clkdiv);
>>>> +	mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv);
>>>
>>> Just for clarification, BIT(15) enables old PWM mode, which ignores
>>> CLKSEL (BIT(3)). Therefore setting BIT(3) does not have any effect and
>>> can be discarded.
>>>
>>> Am I correct? I took mt7623n datasheet for reference.
>>>
>>> Regards,
>>> Matthias
>>>
>> Yes, remove setting bit<3> will not take any effect.
>> PWMCON bit<3> is pwm source clock selecting register.
>> You can check the datasheet of MT7623 for details.
>>
>> Regards
>> Zhi
>>
> Hi Mattias,
> 
> Ignore the above reply, I explain this bit<3> issue for you.
> In the data sheet of MT7623:
> PWMCON bit<3> is PWM source clock selecting register
> 0: CLK=CLKSRC
> 1: CLK=CLKSRC/1625
> for example,
> bit<3>=0, PWM clk source is 26M
> bit<3>=1, PWM clk source is 16K
> The frequency of PWM output will based on this clock source
> if set bit<3>=1, it will cause the frequency of PWM output is not
> correct. I also use the oscilloscope device to measure the output,
> set bit<3>=0, the output meet expectation.
>   

Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

  reply	other threads:[~2017-07-18 16:34 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-06-30  6:05 [PATCH v3 0/6] mediatek: pwm driver add MT2712/MT7622 support Zhi Mao
2017-06-30  6:05 ` Zhi Mao
2017-06-30  6:05 ` Zhi Mao
2017-06-30  6:05 ` [PATCH v3 1/6] pwm: kconfig: modify mediatek information Zhi Mao
2017-06-30  6:05   ` Zhi Mao
2017-06-30  6:05   ` Zhi Mao
2017-08-21  7:31   ` Thierry Reding
2017-08-21  7:31     ` Thierry Reding
2017-06-30  6:05 ` [PATCH v3 2/6] pwm: mediatek: fix pwm source clock selection Zhi Mao
2017-06-30  6:05   ` Zhi Mao
2017-06-30  6:05   ` Zhi Mao
2017-07-05 11:09   ` Matthias Brugger
2017-07-05 11:09     ` Matthias Brugger
     [not found]     ` <d009712e-f0a2-2dc7-2f64-ad8cfa21f98d-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-07-06  6:16       ` Zhi Mao
2017-07-06  6:16         ` Zhi Mao
2017-07-06  6:16         ` Zhi Mao
2017-07-06  6:43         ` Zhi Mao
2017-07-06  6:43           ` Zhi Mao
2017-07-06  6:43           ` Zhi Mao
2017-07-18 16:34           ` Matthias Brugger [this message]
2017-07-18 16:34             ` Matthias Brugger
     [not found]   ` <1498802721-32455-3-git-send-email-zhi.mao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-08-21  7:35     ` Thierry Reding
2017-08-21  7:35       ` Thierry Reding
2017-08-21  7:35       ` Thierry Reding
2017-06-30  6:05 ` [PATCH v3 3/6] pwm: mediatek: fix clock control issue Zhi Mao
2017-06-30  6:05   ` Zhi Mao
2017-06-30  6:05   ` Zhi Mao
     [not found]   ` <1498802721-32455-4-git-send-email-zhi.mao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
2017-08-21  7:47     ` Thierry Reding
2017-08-21  7:47       ` Thierry Reding
2017-08-21  7:47       ` Thierry Reding
2017-06-30  6:05 ` [PATCH v3 4/6] pwm: bindings: add MT2712/MT7622 information Zhi Mao
2017-06-30  6:05   ` Zhi Mao
2017-06-30  6:05   ` Zhi Mao
2017-08-21  7:51   ` Thierry Reding
2017-08-21  7:51     ` Thierry Reding
2017-06-30  6:05 ` [PATCH v3 5/6] pwm: mediatek: add PWM_CLK_DIV_MAX Zhi Mao
2017-06-30  6:05   ` Zhi Mao
2017-06-30  6:05   ` Zhi Mao
2017-08-21  7:58   ` Thierry Reding
2017-08-21  7:58     ` Thierry Reding
2017-06-30  6:05 ` [PATCH v3 6/6] pwm: mediatek: add MT2712/MT7622 support Zhi Mao
2017-06-30  6:05   ` Zhi Mao
2017-06-30  6:05   ` Zhi Mao
2017-08-21  8:05   ` Thierry Reding
2017-08-21  8:05     ` Thierry Reding
2017-08-21  9:05     ` Zhi Mao
2017-08-21  9:05       ` Zhi Mao
2017-08-21  9:05       ` Zhi Mao
2017-07-17  3:16 ` [PATCH v3 0/6] mediatek: pwm driver " Zhi Mao
2017-07-17  3:16   ` Zhi Mao
2017-07-17  3:16   ` Zhi Mao
2017-08-02  7:19   ` Zhi Mao
2017-08-02  7:19     ` Zhi Mao
2017-08-02  7:19     ` Zhi Mao
2017-08-02  8:42     ` John Crispin
2017-08-02  8:42       ` John Crispin
2017-08-02  8:42       ` John Crispin
     [not found]       ` <a9dc58dc-d54c-6e8b-9006-8e8da1535daf-Pj+rj9U5foFAfugRpC6u6w@public.gmane.org>
2017-08-03  9:41         ` Zhi Mao
2017-08-03  9:41           ` Zhi Mao
2017-08-03  9:41           ` Zhi Mao

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