From: Conor.Dooley@microchip.com <Conor.Dooley@microchip.com>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH] riscv: Ensure isa-ext static keys are writable
Date: Tue, 16 Aug 2022 20:14:25 +0000 [thread overview]
Message-ID: <6f392592-e2fd-9fa1-4f43-c79a489d95ae@microchip.com> (raw)
In-Reply-To: <20220816163058.3004536-1-ajones@ventanamicro.com>
On 16/08/2022 17:30, Andrew Jones wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> riscv_isa_ext_keys[] is an array of static keys used in the unified
> ISA extension framework. The keys added to this array may be used
> anywhere, including in modules. Ensure the keys remain writable by
> placing them in the data section.
>
> The need to change riscv_isa_ext_keys[]'s section was found when the
> kvm module started failing to load. Commit 8eb060e10185 ("arch/riscv:
> add Zihintpause support") adds a static branch check for a newly
> added isa-ext key to cpu_relax(), which kvm uses.
>
> Fixes: c360cbec3511 ("riscv: introduce unified static key mechanism for ISA extensions")
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Thanks for the fix!
Still got issues booting mainline on my D1, but this is
no longer one of them :)
> ---
> arch/riscv/kernel/cpufeature.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 553d755483ed..3b5583db9d80 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -28,7 +28,7 @@ unsigned long elf_hwcap __read_mostly;
> /* Host ISA bitmap */
> static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
>
> -__ro_after_init DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
> +DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
> EXPORT_SYMBOL(riscv_isa_ext_keys);
>
> /**
> --
> 2.37.1
>
WARNING: multiple messages have this Message-ID (diff)
From: <Conor.Dooley@microchip.com>
To: <ajones@ventanamicro.com>, <linux-riscv@lists.infradead.org>,
<kvm-riscv@lists.infradead.org>
Cc: <linux-kernel@vger.kernel.org>, <daolu@rivosinc.com>,
<jszhang@kernel.org>, <palmer@dabbelt.com>, <re@w6rz.net>,
<apatel@ventanamicro.com>
Subject: Re: [PATCH] riscv: Ensure isa-ext static keys are writable
Date: Tue, 16 Aug 2022 20:14:25 +0000 [thread overview]
Message-ID: <6f392592-e2fd-9fa1-4f43-c79a489d95ae@microchip.com> (raw)
In-Reply-To: <20220816163058.3004536-1-ajones@ventanamicro.com>
On 16/08/2022 17:30, Andrew Jones wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> riscv_isa_ext_keys[] is an array of static keys used in the unified
> ISA extension framework. The keys added to this array may be used
> anywhere, including in modules. Ensure the keys remain writable by
> placing them in the data section.
>
> The need to change riscv_isa_ext_keys[]'s section was found when the
> kvm module started failing to load. Commit 8eb060e10185 ("arch/riscv:
> add Zihintpause support") adds a static branch check for a newly
> added isa-ext key to cpu_relax(), which kvm uses.
>
> Fixes: c360cbec3511 ("riscv: introduce unified static key mechanism for ISA extensions")
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Thanks for the fix!
Still got issues booting mainline on my D1, but this is
no longer one of them :)
> ---
> arch/riscv/kernel/cpufeature.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 553d755483ed..3b5583db9d80 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -28,7 +28,7 @@ unsigned long elf_hwcap __read_mostly;
> /* Host ISA bitmap */
> static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
>
> -__ro_after_init DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
> +DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
> EXPORT_SYMBOL(riscv_isa_ext_keys);
>
> /**
> --
> 2.37.1
>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: <Conor.Dooley@microchip.com>
To: <ajones@ventanamicro.com>, <linux-riscv@lists.infradead.org>,
<kvm-riscv@lists.infradead.org>
Cc: <linux-kernel@vger.kernel.org>, <daolu@rivosinc.com>,
<jszhang@kernel.org>, <palmer@dabbelt.com>, <re@w6rz.net>,
<apatel@ventanamicro.com>
Subject: Re: [PATCH] riscv: Ensure isa-ext static keys are writable
Date: Tue, 16 Aug 2022 20:14:25 +0000 [thread overview]
Message-ID: <6f392592-e2fd-9fa1-4f43-c79a489d95ae@microchip.com> (raw)
In-Reply-To: <20220816163058.3004536-1-ajones@ventanamicro.com>
On 16/08/2022 17:30, Andrew Jones wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> riscv_isa_ext_keys[] is an array of static keys used in the unified
> ISA extension framework. The keys added to this array may be used
> anywhere, including in modules. Ensure the keys remain writable by
> placing them in the data section.
>
> The need to change riscv_isa_ext_keys[]'s section was found when the
> kvm module started failing to load. Commit 8eb060e10185 ("arch/riscv:
> add Zihintpause support") adds a static branch check for a newly
> added isa-ext key to cpu_relax(), which kvm uses.
>
> Fixes: c360cbec3511 ("riscv: introduce unified static key mechanism for ISA extensions")
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Thanks for the fix!
Still got issues booting mainline on my D1, but this is
no longer one of them :)
> ---
> arch/riscv/kernel/cpufeature.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 553d755483ed..3b5583db9d80 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -28,7 +28,7 @@ unsigned long elf_hwcap __read_mostly;
> /* Host ISA bitmap */
> static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
>
> -__ro_after_init DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
> +DEFINE_STATIC_KEY_ARRAY_FALSE(riscv_isa_ext_keys, RISCV_ISA_EXT_KEY_MAX);
> EXPORT_SYMBOL(riscv_isa_ext_keys);
>
> /**
> --
> 2.37.1
>
next prev parent reply other threads:[~2022-08-16 20:14 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-16 16:30 [PATCH] riscv: Ensure isa-ext static keys are writable Andrew Jones
2022-08-16 16:30 ` Andrew Jones
2022-08-16 16:30 ` Andrew Jones
2022-08-16 16:36 ` Conor.Dooley
2022-08-16 16:36 ` Conor.Dooley
2022-08-16 16:36 ` Conor.Dooley
2022-08-16 16:49 ` Andrew Jones
2022-08-16 16:49 ` Andrew Jones
2022-08-16 16:49 ` Andrew Jones
2022-08-16 16:50 ` Conor.Dooley
2022-08-16 16:50 ` Conor.Dooley
2022-08-16 16:50 ` Conor.Dooley
2022-08-16 20:14 ` Conor.Dooley [this message]
2022-08-16 20:14 ` Conor.Dooley
2022-08-16 20:14 ` Conor.Dooley
2022-08-16 21:20 ` Ron Economos
2022-08-16 21:20 ` Ron Economos
2022-08-16 21:20 ` Ron Economos
2022-08-16 23:41 ` Atish Patra
2022-08-16 23:41 ` Atish Patra
2022-08-16 23:41 ` Atish Patra
2022-08-17 4:29 ` Palmer Dabbelt
2022-08-17 4:29 ` Palmer Dabbelt
2022-08-17 4:29 ` Palmer Dabbelt
2022-08-17 14:30 ` Jisheng Zhang
2022-08-17 14:30 ` Jisheng Zhang
2022-08-17 14:30 ` Jisheng Zhang
2022-08-17 15:31 ` Andrew Jones
2022-08-17 15:31 ` Andrew Jones
2022-08-17 15:31 ` Andrew Jones
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