From: Saif Abrar <saif.abrar@linux.ibm.com>
To: Aditya Gupta <adityag@linux.ibm.com>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, clg@kaod.org,
npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com,
marcel.apfelbaum@gmail.com, cohuck@redhat.com,
pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com,
danielhb413@gmail.com, Harsh Prateek Bora <harshpb@linux.ibm.com>,
jishnu@linux.ibm.com
Subject: Re: [PATCH v4 0/9] pnv/phb4: Update PHB4 to the latest PHB5 spec
Date: Wed, 17 Jun 2026 12:44:20 +0530 [thread overview]
Message-ID: <702f3854-acf8-4955-8436-7296ebdcd2db@linux.ibm.com> (raw)
In-Reply-To: <af4HEUe0erFyaQmB@li-3c92a0cc-27cf-11b2-a85c-b804d9ca68fa.ibm.com>
On 08-05-2026 21:30, Aditya Gupta wrote:
> On 26/03/05 12:09AM, Saif Abrar wrote:
>> Hello,
>>
>> This patchset v4 resolves the tsan build failure seen in
>> https://gitlab.com/mstredhat/qemu/-/jobs/13201554945
>>
>> Few variables were declared directly after a case label inside a switch,
>> causing the compilation failure.
>> These are now moved to the top of the block.
>>
>> This series updates the existing PHB4 model to the latest spec:
>> "Power Systems Host Bridge 5 (PHB5) Functional Specification Version 0.5_00".
>>
>> Updates include the following:
>> - implemented sticky reset logic
>> - implemented read-only, write-only, W1C and WxC logic
>> - return all 1's on read to unimplemented registers
>> - update PCIE registers for link status, speed and width
>> - implement IODA PCT debug table without any functionality
>> - update LSI Source-ID register based on small/big PHB number of interrupts
>>
>> Also, a new testbench for PHB4 model is added that does XSCOM read/writes
>> to various registers of interest and verifies the values.
> Thanks for introducing phb5, saif.
>
> I am currently seeing powernv functional tests failing with the patches
> applied:
>
> 1/16 qemu:func-thorough+func-ppc64-thorough+thorough / func-ppc64-hv SKIP 0.17s 0 subtests passed
> ▶ 2/16 test_powernv.PowernvMachine.test_powernv10 FAIL
> ▶ 2/16 test_powernv.PowernvMachine.test_powernv11 FAIL
> 3/16 qemu:func-thorough+func-ppc64-thorough+thorough / func-ppc64-fadump OK 166.62s 1 subtests passed
> ▶ 2/16 test_powernv.PowernvMachine.test_powernv9 FAIL
> 2/16 qemu:func-thorough+func-ppc64-thorough+thorough / func-ppc64-powernv ERROR 182.93s exit status 1
>
> Able to consistently reproduce it with: 'make check-functional-ppc64 -j4'
>
> Bisect points to below commit:
>
> commit 9b95949d3eb9e733973c692b0e8e0b9043df98e9
> Author: Saif Abrar <saif.abrar@linux.vnet.ibm.com>
> Date: Thu Mar 5 00:09:04 2026 -0600
>
> pnv/phb4: Add reset logic to PHB4
>
> Can you fix the above failure ?
Reverted the updates that were causing the regression.
>
> Meanwhile, will be reviewing the series.
>
> Thanks,
> - Aditya G
Thanks,
Saif
next prev parent reply other threads:[~2026-06-17 7:15 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-30 10:21 [PATCH v2 0/9] pnv/phb4: Update PHB4 to the latest PHB5 spec Saif Abrar
2025-12-30 10:21 ` [PATCH v2 1/9] qtest/phb4: Add testbench for PHB4 Saif Abrar
2025-12-30 10:21 ` [PATCH v2 2/9] pnv/phb4: Add reset logic to PHB4 Saif Abrar
2025-12-30 12:04 ` Michael S. Tsirkin
2025-12-30 10:21 ` [PATCH v2 3/9] pnv/phb4: Implement sticky reset logic in PHB4 Saif Abrar
2025-12-30 10:21 ` [PATCH v2 4/9] pnv/phb4: Implement read-only and write-only bits of registers Saif Abrar
2026-02-04 5:04 ` Michael S. Tsirkin
2026-02-04 5:11 ` Michael S. Tsirkin
2026-02-04 6:42 ` Michael S. Tsirkin
2026-02-09 5:35 ` Saif Abrar
2025-12-30 10:21 ` [PATCH v2 5/9] pnv/phb4: Implement write-clear and return 1's on unimplemented reg read Saif Abrar
2025-12-30 10:21 ` [PATCH v2 6/9] pnv/phb4: Set link-active status in HPSTAT and LMR registers Saif Abrar
2025-12-30 10:21 ` [PATCH v2 7/9] pnv/phb4: Set link speed and width in the DLP training control register Saif Abrar
2025-12-30 10:21 ` [PATCH v2 8/9] pnv/phb4: Implement IODA PCT table Saif Abrar
2025-12-30 10:21 ` [PATCH v2 9/9] pnv/phb4: Mask off LSI Source-ID based on number of interrupts Saif Abrar
2026-02-10 13:40 ` [PATCH v3 0/9] : pnv/phb4: Update PHB4 to the latest PHB5 spec Saif Abrar
2026-02-10 13:40 ` [PATCH v3 1/9] qtest/phb4: Add testbench for PHB4 Saif Abrar
2026-02-10 13:40 ` [PATCH v3 2/9] pnv/phb4: Add reset logic to PHB4 Saif Abrar
2026-02-10 13:40 ` [PATCH v3 3/9] pnv/phb4: Implement sticky reset logic in PHB4 Saif Abrar
2026-02-10 13:40 ` [PATCH v3 4/9] pnv/phb4: Implement read-only and write-only bits of registers Saif Abrar
2026-02-10 13:40 ` [PATCH v3 5/9] pnv/phb4: Implement write-clear and return 1's on unimplemented reg read Saif Abrar
2026-02-10 13:40 ` [PATCH v3 6/9] pnv/phb4: Set link-active status in HPSTAT and LMR registers Saif Abrar
2026-02-10 13:40 ` [PATCH v3 7/9] pnv/phb4: Set link speed and width in the DLP training control register Saif Abrar
2026-02-10 13:40 ` [PATCH v3 8/9] pnv/phb4: Implement IODA PCT table Saif Abrar
2026-02-10 13:40 ` [PATCH v3 9/9] pnv/phb4: Mask off LSI Source-ID based on number of interrupts Saif Abrar
2026-02-10 13:43 ` [PATCH v3 0/9] : pnv/phb4: Update PHB4 to the latest PHB5 spec Michael S. Tsirkin
2026-02-11 5:30 ` Saif Abrar
2026-02-20 16:22 ` Michael S. Tsirkin
[not found] ` <d65ab628-99e3-47af-839c-e059207b692e@linux.vnet.ibm.com>
2026-02-22 14:38 ` Michael S. Tsirkin
2026-03-05 6:09 ` [PATCH v4 0/9] " Saif Abrar
2026-03-05 6:09 ` [PATCH v4 1/9] qtest/phb4: Add testbench for PHB4 Saif Abrar
2026-05-01 13:59 ` Harsh Prateek Bora
2026-06-17 5:54 ` Saif Abrar
2026-05-09 14:33 ` Aditya Gupta
2026-05-09 14:45 ` Aditya Gupta
2026-06-17 5:58 ` Saif Abrar
2026-03-05 6:09 ` [PATCH v4 2/9] pnv/phb4: Add reset logic to PHB4 Saif Abrar
2026-05-01 14:37 ` Harsh Prateek Bora
2026-06-17 6:12 ` Saif Abrar
2026-05-05 14:16 ` Harsh Prateek Bora
2026-06-17 6:13 ` Saif Abrar
2026-05-09 14:42 ` Aditya Gupta
2026-06-17 6:19 ` Saif Abrar
2026-03-05 6:09 ` [PATCH v4 3/9] pnv/phb4: Implement sticky reset logic in PHB4 Saif Abrar
2026-05-05 14:29 ` Harsh Prateek Bora
2026-05-05 15:08 ` Harsh Prateek Bora
2026-06-17 6:22 ` Saif Abrar
2026-06-17 6:20 ` Saif Abrar
2026-05-09 14:48 ` Aditya Gupta
2026-06-17 6:22 ` Saif Abrar
2026-03-05 6:09 ` [PATCH v4 4/9] pnv/phb4: Implement read-only and write-only bits of registers Saif Abrar
2026-05-05 14:55 ` Harsh Prateek Bora
2026-06-17 6:23 ` Saif Abrar
2026-05-09 14:54 ` Aditya Gupta
2026-06-17 6:25 ` Saif Abrar
2026-03-05 6:09 ` [PATCH v4 5/9] pnv/phb4: Implement write-clear and return 1's on unimplemented reg read Saif Abrar
2026-05-09 14:56 ` Aditya Gupta
2026-06-17 6:28 ` Saif Abrar
2026-03-05 6:09 ` [PATCH v4 6/9] pnv/phb4: Set link-active status in HPSTAT and LMR registers Saif Abrar
2026-05-05 17:46 ` Harsh Prateek Bora
2026-06-17 6:29 ` Saif Abrar
2026-05-09 15:00 ` Aditya Gupta
2026-06-17 6:32 ` Saif Abrar
2026-03-05 6:09 ` [PATCH v4 7/9] pnv/phb4: Set link speed and width in the DLP training control register Saif Abrar
2026-05-09 15:02 ` Aditya Gupta
2026-06-17 7:11 ` Saif Abrar
2026-03-05 6:09 ` [PATCH v4 8/9] pnv/phb4: Implement IODA PCT table Saif Abrar
2026-05-09 15:03 ` Aditya Gupta
2026-06-17 7:12 ` Saif Abrar
2026-05-11 7:24 ` Jishnu Warrier
2026-06-17 7:13 ` Saif Abrar
2026-03-05 6:09 ` [PATCH v4 9/9] pnv/phb4: Mask off LSI Source-ID based on number of interrupts Saif Abrar
2026-05-09 15:04 ` Aditya Gupta
2026-06-17 7:15 ` Saif Abrar
2026-05-11 8:46 ` Jishnu Warrier
2026-06-17 7:16 ` Saif Abrar
2026-05-08 16:00 ` [PATCH v4 0/9] pnv/phb4: Update PHB4 to the latest PHB5 spec Aditya Gupta
2026-06-17 7:14 ` Saif Abrar [this message]
2026-05-19 5:52 ` Saif Abrar
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