[RFC 1/2] config/arm: add Neoverse V2 part number

[RFC 1/2] config/arm: add Neoverse V2 part number

[Honnappa Nagarahalli]

Add Arm Neoverse V2 part number

Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
---
 config/arm/meson.build | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 36f21d2259..18b595ead1 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -100,6 +100,16 @@ part_number_config_arm = {
             ['RTE_MAX_LCORE', 128],
             ['RTE_MAX_NUMA_NODES', 2]
         ]
+    },
+    '0xd4f': {
+        'march_features': ['sve2'],
+        'compiler_options': ['-mcpu=neoverse-v2'],
+        'flags': [
+            ['RTE_MACHINE', '"neoverse-v2"'],
+            ['RTE_ARM_FEATURE_ATOMICS', true],
+            ['RTE_MAX_LCORE', 144],
+            ['RTE_MAX_NUMA_NODES', 2]
+        ]
     }
 }
 implementer_arm = {
-- 
2.25.1

[RFC 2/2] config/arm: add NVIDIA Grace CPU

[Honnappa Nagarahalli]

Add meson build configuration for NVIDIA Grace platform
with 64-bit Arm Neoverse V2 cores.

Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
---
 config/arm/arm64_grace_linux_gcc | 16 ++++++++++++++++
 config/arm/meson.build           | 10 ++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 config/arm/arm64_grace_linux_gcc

diff --git a/config/arm/arm64_grace_linux_gcc b/config/arm/arm64_grace_linux_gcc
new file mode 100644
index 0000000000..bde55b17a8
--- /dev/null
+++ b/config/arm/arm64_grace_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = ['ccache', 'aarch64-linux-gnu-gcc']
+cpp = ['ccache', 'aarch64-linux-gnu-g++']
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pkgconfig = 'aarch64-linux-gnu-pkg-config'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv9-a'
+endian = 'little'
+
+[properties]
+platform = 'grace'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 18b595ead1..345a9dbf6b 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -424,6 +424,14 @@ soc_tys2500 = {
     'numa': true
 }
 
+soc_grace = {
+    'description': 'NVIDIA Grace',
+    'implementer': '0x41',
+    'part_number': '0xd4f',
+    'extra_march_features': ['crypto'],
+    'numa': true
+}
+
 soc_graviton2 = {
     'description': 'AWS Graviton2',
     'implementer': '0x41',
@@ -544,6 +552,7 @@ dpaa:            NXP DPAA
 emag:            Ampere eMAG
 ft2000plus:      Phytium FT-2000+
 tys2500:         Phytium TengYun S2500
+grace:           NVIDIA Grace
 graviton2:       AWS Graviton2
 graviton3:       AWS Graviton3
 hip10:           HiSilicon HIP10
@@ -575,6 +584,7 @@ socs = {
     'emag': soc_emag,
     'ft2000plus': soc_ft2000plus,
     'tys2500': soc_tys2500,
+    'grace': soc_grace,
     'graviton2': soc_graviton2,
     'graviton3': soc_graviton3,
     'hip10': soc_hip10,
-- 
2.25.1

Re: [RFC 2/2] config/arm: add NVIDIA Grace CPU

[Ruifeng Wang]

On 2024/1/18 10:32 AM, Honnappa Nagarahalli wrote:
> Add meson build configuration for NVIDIA Grace platform
> with 64-bit Arm Neoverse V2 cores.
> 
> Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> ---
>   config/arm/arm64_grace_linux_gcc | 16 ++++++++++++++++
>   config/arm/meson.build           | 10 ++++++++++
>   2 files changed, 26 insertions(+)
>   create mode 100644 config/arm/arm64_grace_linux_gcc
> 
> diff --git a/config/arm/arm64_grace_linux_gcc b/config/arm/arm64_grace_linux_gcc
> new file mode 100644
> index 0000000000..bde55b17a8
> --- /dev/null
> +++ b/config/arm/arm64_grace_linux_gcc
> @@ -0,0 +1,16 @@
> +[binaries]
> +c = ['ccache', 'aarch64-linux-gnu-gcc']
> +cpp = ['ccache', 'aarch64-linux-gnu-g++']
> +ar = 'aarch64-linux-gnu-gcc-ar'
> +strip = 'aarch64-linux-gnu-strip'
> +pkgconfig = 'aarch64-linux-gnu-pkg-config'
> +pcap-config = ''
> +
> +[host_machine]
> +system = 'linux'
> +cpu_family = 'aarch64'
> +cpu = 'armv9-a'
> +endian = 'little'
> +
> +[properties]
> +platform = 'grace'
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 18b595ead1..345a9dbf6b 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -424,6 +424,14 @@ soc_tys2500 = {
>       'numa': true
>   }
>   
> +soc_grace = {
> +    'description': 'NVIDIA Grace',
> +    'implementer': '0x41',
> +    'part_number': '0xd4f',
> +    'extra_march_features': ['crypto'],
> +    'numa': true
> +}
> +
>   soc_graviton2 = {
>       'description': 'AWS Graviton2',
>       'implementer': '0x41',
> @@ -544,6 +552,7 @@ dpaa:            NXP DPAA
>   emag:            Ampere eMAG
>   ft2000plus:      Phytium FT-2000+
>   tys2500:         Phytium TengYun S2500
> +grace:           NVIDIA Grace
>   graviton2:       AWS Graviton2
>   graviton3:       AWS Graviton3
>   hip10:           HiSilicon HIP10
> @@ -575,6 +584,7 @@ socs = {
>       'emag': soc_emag,
>       'ft2000plus': soc_ft2000plus,
>       'tys2500': soc_tys2500,
> +    'grace': soc_grace,
>       'graviton2': soc_graviton2,
>       'graviton3': soc_graviton3,
>       'hip10': soc_hip10,
Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>

Re: [RFC 1/2] config/arm: add Neoverse V2 part number

[Ruifeng Wang]

On 2024/1/18 10:32 AM, Honnappa Nagarahalli wrote:
> Add Arm Neoverse V2 part number
> 
> Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> ---
>   config/arm/meson.build | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 36f21d2259..18b595ead1 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -100,6 +100,16 @@ part_number_config_arm = {
>               ['RTE_MAX_LCORE', 128],
>               ['RTE_MAX_NUMA_NODES', 2]
>           ]
> +    },
> +    '0xd4f': {
> +        'march_features': ['sve2'],
> +        'compiler_options': ['-mcpu=neoverse-v2'],
> +        'flags': [
> +            ['RTE_MACHINE', '"neoverse-v2"'],
> +            ['RTE_ARM_FEATURE_ATOMICS', true],
> +            ['RTE_MAX_LCORE', 144],
> +            ['RTE_MAX_NUMA_NODES', 2]
> +        ]
>       }
>   }
>   implementer_arm = {
Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>

[PATCH v2 1/4] config/arm: add Neoverse V2 part number

[Honnappa Nagarahalli]

Add Arm Neoverse V2 CPU part number

Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Wathsala Vithanage <wathsala.vithanage@arm.com>
---
 config/arm/meson.build | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 36f21d2259..18b595ead1 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -100,6 +100,16 @@ part_number_config_arm = {
             ['RTE_MAX_LCORE', 128],
             ['RTE_MAX_NUMA_NODES', 2]
         ]
+    },
+    '0xd4f': {
+        'march_features': ['sve2'],
+        'compiler_options': ['-mcpu=neoverse-v2'],
+        'flags': [
+            ['RTE_MACHINE', '"neoverse-v2"'],
+            ['RTE_ARM_FEATURE_ATOMICS', true],
+            ['RTE_MAX_LCORE', 144],
+            ['RTE_MAX_NUMA_NODES', 2]
+        ]
     }
 }
 implementer_arm = {
-- 
2.34.1

[PATCH v2 2/4] config/arm: add generic V2 SoC

[Honnappa Nagarahalli]

Add generic V2 CPU SoC. This will allow for compiling a binary
that will run on any SoC that uses V2 CPU.

Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Wathsala Vithanage <wathsala.vithanage@arm.com>
---
 config/arm/arm64_v2_linux_gcc | 16 ++++++++++++++++
 config/arm/meson.build        |  9 +++++++++
 2 files changed, 25 insertions(+)
 create mode 100644 config/arm/arm64_v2_linux_gcc

diff --git a/config/arm/arm64_v2_linux_gcc b/config/arm/arm64_v2_linux_gcc
new file mode 100644
index 0000000000..50d9be3da3
--- /dev/null
+++ b/config/arm/arm64_v2_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = ['ccache', 'aarch64-linux-gnu-gcc']
+cpp = ['ccache', 'aarch64-linux-gnu-g++']
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pkgconfig = 'aarch64-linux-gnu-pkg-config'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv9-a'
+endian = 'little'
+
+[properties]
+platform = 'v2'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 18b595ead1..f096ed9ebf 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -527,6 +527,13 @@ soc_bluefield3 = {
    'numa': false
 }
 
+soc_v2 = {
+    'description': 'Arm Neoverse V2',
+    'implementer': '0x41',
+    'part_number': '0xd4f',
+    'numa': true
+}
+
 '''
 Start of SoCs list
 generic:         Generic un-optimized build for armv8 aarch64 execution mode.
@@ -555,6 +562,7 @@ stingray:        Broadcom Stingray
 thunderx2:       Marvell ThunderX2 T99
 thunderxt88:     Marvell ThunderX T88
 thunderxt83:     Marvell ThunderX T83
+v2:              Arm Neoverse V2
 End of SoCs list
 '''
 # The string above is included in the documentation, keep it in sync with the
@@ -586,6 +594,7 @@ socs = {
     'thunderx2': soc_thunderx2,
     'thunderxt88': soc_thunderxt88,
     'thunderxt83': soc_thunderxt83,
+    'v2': soc_v2,
 }
 
 dpdk_conf.set('RTE_ARCH_ARM', 1)
-- 
2.34.1

Re: [PATCH v2 2/4] config/arm: add generic V2 SoC

[Thomas Monjalon]

20/02/2024 02:45, Honnappa Nagarahalli:
> Add generic V2 CPU SoC. This will allow for compiling a binary
> that will run on any SoC that uses V2 CPU.
[...]
> +soc_v2 = {
> +    'description': 'Arm Neoverse V2',
> +    'implementer': '0x41',
> +    'part_number': '0xd4f',
> +    'numa': true
> +}
[...]
>  thunderxt88:     Marvell ThunderX T88
>  thunderxt83:     Marvell ThunderX T83
> +v2:              Arm Neoverse V2

Why just "v2" and not "neoversev2"?

Is it a new Arm naming?
If yes, why not just "2" ;)
Last question: what is best between Arm V2 and Armv7? answer is aarchv2 :D
Sorry I like having fun with Arm naming.

Re: [PATCH v2 2/4] config/arm: add generic V2 SoC

[Honnappa Nagarahalli]

> On Feb 22, 2024, at 1:08 AM, Thomas Monjalon <thomas@monjalon.net> wrote:
> 
> 20/02/2024 02:45, Honnappa Nagarahalli:
>> Add generic V2 CPU SoC. This will allow for compiling a binary
>> that will run on any SoC that uses V2 CPU.
> [...]
>> +soc_v2 = {
>> +    'description': 'Arm Neoverse V2',
>> +    'implementer': '0x41',
>> +    'part_number': '0xd4f',
>> +    'numa': true
>> +}
> [...]
>> thunderxt88:     Marvell ThunderX T88
>> thunderxt83:     Marvell ThunderX T83
>> +v2:              Arm Neoverse V2
> 
> Why just "v2" and not "neoversev2”?
This is what was done for N2, so just keeping it consistent

> 
> Is it a new Arm naming?
No. ’Neoverse’ is the brand name that encompasses all the products for infrastructure market. CPUs are one of the products under Neoverse brand name. There are 2 series of CPUs (targeting 2 different PPAs) - N series and V series. N2 and V2 are the second generation of CPUs in those series.

> If yes, why not just "2" ;)
> Last question: what is best between Arm V2 and Armv7? answer is aarchv2 :D
ArmV7/ArmV8/ArmV9 are architecture revisions. There is no ArmV2 architecture.

Aarch32/Aarch64 are architecture states. For ex: N1 supported Aarch32 to run 32b applications as well as Aarch64 to run 64b applications. The later cores just support Aarch64 state and one can run only 64b applications.

> Sorry I like having fun with Arm naming.
No worries, it can be confusing. I hope the above explanation helps.

You have to pin this email for several months to be able to remember this :)
> 
> 

[PATCH v2 3/4] config/arm: add NVIDIA Grace CPU

[Honnappa Nagarahalli]

Add meson build configuration for NVIDIA Grace platform
with 64-bit Arm Neoverse V2 cores.

Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
Reviewed-by: Wathsala Vithanage <wathsala.vithanage@arm.com>
---
 config/arm/arm64_grace_linux_gcc | 16 ++++++++++++++++
 config/arm/meson.build           | 10 ++++++++++
 2 files changed, 26 insertions(+)
 create mode 100644 config/arm/arm64_grace_linux_gcc

diff --git a/config/arm/arm64_grace_linux_gcc b/config/arm/arm64_grace_linux_gcc
new file mode 100644
index 0000000000..bde55b17a8
--- /dev/null
+++ b/config/arm/arm64_grace_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = ['ccache', 'aarch64-linux-gnu-gcc']
+cpp = ['ccache', 'aarch64-linux-gnu-g++']
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pkgconfig = 'aarch64-linux-gnu-pkg-config'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv9-a'
+endian = 'little'
+
+[properties]
+platform = 'grace'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index f096ed9ebf..606d8942ca 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -424,6 +424,14 @@ soc_tys2500 = {
     'numa': true
 }
 
+soc_grace = {
+    'description': 'NVIDIA Grace',
+    'implementer': '0x41',
+    'part_number': '0xd4f',
+    'extra_march_features': ['crypto'],
+    'numa': true
+}
+
 soc_graviton2 = {
     'description': 'AWS Graviton2',
     'implementer': '0x41',
@@ -551,6 +559,7 @@ dpaa:            NXP DPAA
 emag:            Ampere eMAG
 ft2000plus:      Phytium FT-2000+
 tys2500:         Phytium TengYun S2500
+grace:           NVIDIA Grace
 graviton2:       AWS Graviton2
 graviton3:       AWS Graviton3
 hip10:           HiSilicon HIP10
@@ -583,6 +592,7 @@ socs = {
     'emag': soc_emag,
     'ft2000plus': soc_ft2000plus,
     'tys2500': soc_tys2500,
+    'grace': soc_grace,
     'graviton2': soc_graviton2,
     'graviton3': soc_graviton3,
     'hip10': soc_hip10,
-- 
2.34.1

[PATCH v2 4/4] config/arm: add AWS Graviton4 CPU

[Honnappa Nagarahalli]

Add meson build configuration for AWS Graviton4 platform
with 64-bit Arm Neoverse V2 cores.

Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Reviewed-by: Wathsala Vithanage <wathsala.vithanage@arm.com>
---
 config/arm/arm64_graviton4_linux_gcc | 16 ++++++++++++++++
 config/arm/meson.build               | 14 ++++++++++++++
 2 files changed, 30 insertions(+)
 create mode 100644 config/arm/arm64_graviton4_linux_gcc

diff --git a/config/arm/arm64_graviton4_linux_gcc b/config/arm/arm64_graviton4_linux_gcc
new file mode 100644
index 0000000000..839224bca7
--- /dev/null
+++ b/config/arm/arm64_graviton4_linux_gcc
@@ -0,0 +1,16 @@
+[binaries]
+c = ['ccache', 'aarch64-linux-gnu-gcc']
+cpp = ['ccache', 'aarch64-linux-gnu-g++']
+ar = 'aarch64-linux-gnu-gcc-ar'
+strip = 'aarch64-linux-gnu-strip'
+pkgconfig = 'aarch64-linux-gnu-pkg-config'
+pcap-config = ''
+
+[host_machine]
+system = 'linux'
+cpu_family = 'aarch64'
+cpu = 'armv9-a'
+endian = 'little'
+
+[properties]
+platform = 'graviton4'
diff --git a/config/arm/meson.build b/config/arm/meson.build
index 606d8942ca..075d6d8e88 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -447,6 +447,18 @@ soc_graviton3 = {
     'numa': false
 }
 
+soc_graviton4 = {
+    'description': 'AWS Graviton4',
+    'implementer': '0x41',
+    'part_number': '0xd4f',
+    'extra_march_features': ['crypto'],
+    'flags': [
+        ['RTE_MAX_LCORE', 96],
+        ['RTE_MAX_NUMA_NODES', 1]
+    ],
+    'numa': false
+}
+
 soc_hip10 = {
     'description': 'HiSilicon HIP10',
     'implementer': '0x48',
@@ -562,6 +574,7 @@ tys2500:         Phytium TengYun S2500
 grace:           NVIDIA Grace
 graviton2:       AWS Graviton2
 graviton3:       AWS Graviton3
+graviton4:       AWS Graviton4
 hip10:           HiSilicon HIP10
 kunpeng920:      HiSilicon Kunpeng 920
 kunpeng930:      HiSilicon Kunpeng 930
@@ -595,6 +608,7 @@ socs = {
     'grace': soc_grace,
     'graviton2': soc_graviton2,
     'graviton3': soc_graviton3,
+    'graviton4': soc_graviton4,
     'hip10': soc_hip10,
     'kunpeng920': soc_kunpeng920,
     'kunpeng930': soc_kunpeng930,
-- 
2.34.1

Re: [PATCH v2 1/4] config/arm: add Neoverse V2 part number

[Thomas Monjalon]

20/02/2024 02:45, Honnappa Nagarahalli:
> Add Arm Neoverse V2 CPU part number
> 
> Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
> Acked-by: Ruifeng Wang <ruifeng.wang@arm.com>
> Reviewed-by: Wathsala Vithanage <wathsala.vithanage@arm.com>

Series applied, thanks.