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From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
	alistair.francis@wdc.com, dbarboza@ventanamicro.com,
	liwei1518@gmail.com, bmeng.cn@gmail.com,
	TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: Re: [PATCH v1 07/15] tcg/riscv: Implement vector mov/dup{m/i}
Date: Thu, 15 Aug 2024 18:49:22 +0800	[thread overview]
Message-ID: <70a2e212-e2c5-4221-87cc-6ff371b5f509@linux.alibaba.com> (raw)
In-Reply-To: <21210e0f-457e-4858-befc-f869984d3315@linaro.org>


On 2024/8/14 17:11, Richard Henderson wrote:
> On 8/13/24 21:34, LIU Zhiwei wrote:
>> @@ -641,6 +645,13 @@ static bool tcg_out_mov(TCGContext *s, TCGType 
>> type, TCGReg ret, TCGReg arg)
>>       case TCG_TYPE_I64:
>>           tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
>>           break;
>> +    case TCG_TYPE_V64:
>> +    case TCG_TYPE_V128:
>> +    case TCG_TYPE_V256:
>> +        tcg_debug_assert(ret > TCG_REG_V0 && arg > TCG_REG_V0);
>> +        tcg_target_set_vec_config(s, type, prev_vece);
>> +        tcg_out_opc_vv(s, OPC_VMV_V_V, ret, TCG_REG_V0, arg, true);
>
> I suggest these asserts be in tcg_out_opc_*
> That way you don't need to replicate to all uses.
OK.
>
>> +static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, 
>> unsigned vece,
>> +                                   TCGReg dst, TCGReg src)
>
> Oh, please drop all of the inline markup, from all patches.
> Let the compiler decide.
>
OK.
>> +static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, 
>> unsigned vece,
>> +                                    TCGReg dst, TCGReg base, 
>> intptr_t offset)
>> +{
>> +    tcg_out_ld(s, TCG_TYPE_REG, TCG_REG_TMP0, base, offset);
>> +    return tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0);
>> +}
>
> Is this really better than using strided load with rs2 = r0?

It depends.  For our test board, it is.

Thanks,
Zhiwei

>
>
> r~


  reply	other threads:[~2024-08-15 10:50 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-13 11:34 [PATCH v1 00/15] tcg/riscv: Add support for vector LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 01/15] util: Add RISC-V vector extension probe in cpuinfo LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 02/15] tcg/op-gvec: Fix iteration step in 32-bit operation LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 03/15] tcg: Fix register allocation constraints LIU Zhiwei
2024-08-13 11:52   ` Richard Henderson
2024-08-14  0:58     ` LIU Zhiwei
2024-08-14  2:04       ` Richard Henderson
2024-08-14  2:27         ` LIU Zhiwei
2024-08-14  3:08           ` Richard Henderson
2024-08-14  3:30             ` LIU Zhiwei
2024-08-14  4:18               ` Richard Henderson
2024-08-14  7:47                 ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 04/15] tcg/riscv: Add basic support for vector LIU Zhiwei
2024-08-13 12:19   ` Richard Henderson
2024-08-13 11:34 ` [PATCH v1 05/15] tcg/riscv: Add riscv vset{i}vli support LIU Zhiwei
2024-08-14  8:24   ` Richard Henderson
2024-08-19  1:34     ` LIU Zhiwei
2024-08-19  2:35       ` Richard Henderson
2024-08-19  2:53         ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 06/15] tcg/riscv: Implement vector load/store LIU Zhiwei
2024-08-14  9:01   ` Richard Henderson
2024-08-19  1:41     ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 07/15] tcg/riscv: Implement vector mov/dup{m/i} LIU Zhiwei
2024-08-14  9:11   ` Richard Henderson
2024-08-15 10:49     ` LIU Zhiwei [this message]
2024-08-20  9:00   ` Richard Henderson
2024-08-20  9:26     ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 08/15] tcg/riscv: Add support for basic vector opcodes LIU Zhiwei
2024-08-14  9:13   ` Richard Henderson
2024-08-20  1:56     ` LIU Zhiwei
2024-08-14  9:17   ` Richard Henderson
2024-08-20  1:57     ` LIU Zhiwei
2024-08-20  5:14       ` Richard Henderson
2024-08-13 11:34 ` [PATCH v1 09/15] tcg/riscv: Implement vector cmp ops LIU Zhiwei
2024-08-14  9:39   ` Richard Henderson
2024-08-27  7:50     ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 10/15] tcg/riscv: Implement vector not/neg ops LIU Zhiwei
2024-08-14  9:45   ` Richard Henderson
2024-08-27  7:55     ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 11/15] tcg/riscv: Implement vector sat/mul ops LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 12/15] tcg/riscv: Implement vector min/max ops LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 13/15] tcg/riscv: Implement vector shs/v ops LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 14/15] tcg/riscv: Implement vector roti/v/x shi ops LIU Zhiwei
2024-08-14  9:55   ` Richard Henderson
2024-08-27  7:57     ` LIU Zhiwei
2024-08-13 11:34 ` [PATCH v1 15/15] tcg/riscv: Enable vector TCG host-native LIU Zhiwei
2024-08-14 10:15   ` Richard Henderson
2024-08-27  8:31     ` LIU Zhiwei
2024-08-28 23:35       ` Richard Henderson

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