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From: Jan Beulich <jbeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: "Roger Pau Monné" <roger.pau@citrix.com>,
	"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Subject: Re: [PATCH v9 07/10] VMX: support MSR-IMM
Date: Thu, 27 Nov 2025 09:18:04 +0100	[thread overview]
Message-ID: <726f1d23-343b-4151-8c8f-a7b9ee3e08a1@suse.com> (raw)
In-Reply-To: <0b20af96-bfef-43b1-a22a-db85a18b849d@citrix.com>

On 26.11.2025 19:50, Andrew Cooper wrote:
> On 24/11/2025 3:00 pm, Jan Beulich wrote:
>> Hook up the new VM exit codes and handle guest uses of the insns.
>>
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>> ---
>> v9: New.
>> ---
>> The lack of an enable bit is concerning; at least for the nested case
>> that's a security issue afaict (when L0 isn't aware of the insns, or more
>> specifically the exit codes).
> 
> This is why we need support statements of new CPUs.

I hope you don't mean the lack thereof to be a blocking factor for this
change?

> Intel say that unknown VMExits turning into #UD is the expected course
> of action.  That covers all of these cases which don't have an explicit
> enable.

Do you have a pointer?

> This is better than our current behaviour, which is non-architectural
> for supervisor code and practically the most unhelpful course of action
> going.
> 
> Obviously, logic turning on a new feature is expected to handle all the
> VMExit cases it can produce.

What you say here ...

> The corollary for nested virt is that L0 must never make a Virtual
> VMExit with case that isn't enabled.  Combined with #UD in the unknown
> case, that covers things reasonably well.
> 
>> --- a/xen/arch/x86/domain.c
>> +++ b/xen/arch/x86/domain.c
>> @@ -453,7 +453,7 @@ void domain_cpu_policy_changed(struct do
>>      }
>>  
>>      /* Nested doesn't have the necessary processing, yet. */
>> -    if ( nestedhvm_enabled(d) && p->feat.user_msr )
>> +    if ( nestedhvm_enabled(d) && (p->feat.user_msr || p->feat.msr_imm) )
>>          return /* -EINVAL */;
> 
> What processing is missing?  (Aside from correcting the unknown case.)

... is what would need doing for this check to disappear. Going the #UD
route looks to make sense, but it still wouldn't feel quite right then
to drop this check. If we expose the feature, we shouldn't convert
respective exits to #UD. They aren't "unknown" (anymore) after all.

And then again the question is: Are you expecting me to deal with
switching to the #UD model as a prereq (if, as per above, that's
relevant at all here)? If so, I have to admit that it's not quite clear
to me what exactly this would be meant to look like: Alter the default
cases of the big switch()es in both the normal and nested exit handlers?
Or merely the latter?

>> --- a/xen/arch/x86/hvm/vmx/vmx.c
>> +++ b/xen/arch/x86/hvm/vmx/vmx.c
>> @@ -4762,6 +4762,7 @@ void asmlinkage vmx_vmexit_handler(struc
>>          break;
>>  
>>      case EXIT_REASON_URDMSR:
>> +    case EXIT_REASON_RDMSR_IMM:
> 
> Instructions which aren't enumerated in CPUID have reserved behaviour.
> 
> The exit handler needs to check cp->feat.msr_imm and inject #UD.
> 
> It's not perfect; un-intercepted MSRs will happen to execute correctly
> on capable hardware, but most MSRs are not intercepted and it's far
> closer to adequate behaviour than omitting the #UD check.

Hmm, okay, I can certainly do it this way.

Jan


  reply	other threads:[~2025-11-27  8:18 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-24 14:56 [PATCH v9 10/10] x86emul: misc additions Jan Beulich
2025-11-24 14:57 ` [PATCH v9 01/10] x86emul: support LKGS Jan Beulich
2025-11-24 14:58 ` [PATCH v9 02/10] x86emul+VMX: support {RD,WR}MSRLIST Jan Beulich
2025-11-24 14:58 ` [PATCH v9 03/10] x86emul: support USER_MSR instructions Jan Beulich
2025-11-24 14:59 ` [PATCH v9 04/10] x86/cpu-policy: re-arrange no-VMX logic Jan Beulich
2026-04-07 21:58   ` Andrew Cooper
2026-04-08  6:09     ` Jan Beulich
2025-11-24 15:00 ` [PATCH v9 05/10] VMX: support USER-MSR Jan Beulich
2025-11-24 15:00 ` [PATCH v9 06/10] x86emul: support MSR_IMM instructions Jan Beulich
2025-11-24 15:00 ` [PATCH v9 07/10] VMX: support MSR-IMM Jan Beulich
2025-11-26 18:50   ` Andrew Cooper
2025-11-27  8:18     ` Jan Beulich [this message]
2025-11-24 15:01 ` [PATCH v9 08/10] x86emul: support non-SIMD MOVRS Jan Beulich
2025-11-24 15:01 ` [PATCH v9 09/10] x86: use / "support" UDB Jan Beulich
2025-12-05 12:01   ` Andrew Cooper
2025-12-05 12:40     ` Andrew Cooper
2025-12-05 13:13       ` Jan Beulich
2025-12-05 13:15         ` Andrew Cooper
2025-12-05 13:15       ` Jan Beulich
2025-12-05 13:35         ` Andrew Cooper
2025-12-05 13:09     ` Jan Beulich
2025-11-24 15:02 ` [PATCH v9 10/10] x86emul: support AVX512-BMM Jan Beulich
2025-12-05 12:33   ` Andrew Cooper
2025-12-05 12:47     ` Jan Beulich
2026-04-07 15:11       ` Andrew Cooper
2025-11-24 15:03 ` [PATCH v9 00/10] x86emul: misc additions Jan Beulich

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