From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: David Virag <virag.david003@gmail.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>,
Tomasz Figa <tomasz.figa@gmail.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
Alim Akhtar <alim.akhtar@samsung.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [RESEND PATCH] clk: samsung: exynos7885: Correct "div4" clock parents
Date: Thu, 13 Oct 2022 10:35:54 -0400 [thread overview]
Message-ID: <7315338a-762f-51a4-d26f-d94de71dfcf2@linaro.org> (raw)
In-Reply-To: <20221013151341.151208-1-virag.david003@gmail.com>
On 13/10/2022 11:13, David Virag wrote:
> "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
> 2 to achieve a by 4 division, thus their parents are the respective
> "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
> This leads to the kernel thinking "div4"s and everything under them run
> at 2x the clock speed. Fix this.
>
> Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver")
> Signed-off-by: David Virag <virag.david003@gmail.com>
> ---
Looks good, I'll take it after merge window.
Best regards,
Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: David Virag <virag.david003@gmail.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>,
Tomasz Figa <tomasz.figa@gmail.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
Alim Akhtar <alim.akhtar@samsung.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [RESEND PATCH] clk: samsung: exynos7885: Correct "div4" clock parents
Date: Thu, 13 Oct 2022 10:35:54 -0400 [thread overview]
Message-ID: <7315338a-762f-51a4-d26f-d94de71dfcf2@linaro.org> (raw)
In-Reply-To: <20221013151341.151208-1-virag.david003@gmail.com>
On 13/10/2022 11:13, David Virag wrote:
> "div4" DIVs which divide PLLs by 4 are actually dividing "div2" DIVs by
> 2 to achieve a by 4 division, thus their parents are the respective
> "div2" DIVs. These DIVs were mistakenly set to have the PLLs as parents.
> This leads to the kernel thinking "div4"s and everything under them run
> at 2x the clock speed. Fix this.
>
> Fixes: 45bd8166a1d8 ("clk: samsung: Add initial Exynos7885 clock driver")
> Signed-off-by: David Virag <virag.david003@gmail.com>
> ---
Looks good, I'll take it after merge window.
Best regards,
Krzysztof
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next prev parent reply other threads:[~2022-10-13 14:36 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-13 15:13 [RESEND PATCH] clk: samsung: exynos7885: Correct "div4" clock parents David Virag
2022-10-13 15:13 ` David Virag
2022-10-13 14:35 ` Krzysztof Kozlowski [this message]
2022-10-13 14:35 ` Krzysztof Kozlowski
2022-10-13 19:36 ` Chanwoo Choi
2022-10-13 19:36 ` Chanwoo Choi
2022-10-18 13:19 ` Krzysztof Kozlowski
2022-10-18 13:19 ` Krzysztof Kozlowski
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