[PATCH] Handle instruction cache maintenance fault properly

[PATCH] Handle instruction cache maintenance fault properly

[Kirill A. Shutemov]

Between "clean D line..." and "invalidate I line" operations in
v7_coherent_user_range(), the memory page may get swapped out.
And the fault on "invalidate I line" could not be properly handled
causing the oops.

The patch adds the missing handling for "instruction cache
maintenance fault". Let's handle it as translation fault.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
---
 arch/arm/mm/fault.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 9d40c34..8924617 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -463,7 +463,7 @@ static struct fsr_info {
 	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
 	{ do_bad,		SIGKILL, 0,		"terminal exception"		   },
 	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
-	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
+	{ do_translation_fault,	SIGSEGV, SEGV_MAPPER,	"I-cache maintenance
fault"	   },
 	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"section translation
fault"	   },
 	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
 	{ do_page_fault,	SIGSEGV, SEGV_MAPERR,	"page translation fault"	   },
-- 
1.7.0.4

[PATCH] Handle instruction cache maintenance fault properly

[Kirill A. Shutemov]

Between "clean D line..." and "invalidate I line" operations in
v7_coherent_user_range(), the memory page may get swapped out.
And the fault on "invalidate I line" could not be properly handled
causing the oops.

The patch adds the missing handling for "instruction cache
maintenance fault". Let's handle it as translation fault.

Signed-off-by: Siarhei Siamashka <siarhei.siamashka@nokia.com>
Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
---
 arch/arm/mm/fault.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 9d40c34..8924617 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -463,7 +463,7 @@ static struct fsr_info {
 	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
 	{ do_bad,		SIGKILL, 0,		"terminal exception"		   },
 	{ do_bad,		SIGILL,	 BUS_ADRALN,	"alignment exception"		   },
-	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
+	{ do_translation_fault,	SIGSEGV, SEGV_MAPPER,	"I-cache maintenance
fault"	   },
 	{ do_translation_fault,	SIGSEGV, SEGV_MAPERR,	"section translation
fault"	   },
 	{ do_bad,		SIGBUS,	 0,		"external abort on linefetch"	   },
 	{ do_page_fault,	SIGSEGV, SEGV_MAPERR,	"page translation fault"	   },
-- 
1.7.0.4

[PATCH] Handle instruction cache maintenance fault properly

[Russell King - ARM Linux]

On Mon, May 10, 2010 at 04:07:57PM +0300, Kirill A. Shutemov wrote:
> Between "clean D line..." and "invalidate I line" operations in
> v7_coherent_user_range(), the memory page may get swapped out.
> And the fault on "invalidate I line" could not be properly handled
> causing the oops.

You have to be very careful when doing this kind of change - you need to
review the behaviour of previous ARMs to ensure that you don't throw the
CPU into an infinite loop when an "external abort on linefetch" occurs.

With older CPUs, an "external abort on linefetch" is most probably fatal
to the process and can never be recovered.

Re: [PATCH] Handle instruction cache maintenance fault properly

[Russell King - ARM Linux]

On Mon, May 10, 2010 at 04:07:57PM +0300, Kirill A. Shutemov wrote:
> Between "clean D line..." and "invalidate I line" operations in
> v7_coherent_user_range(), the memory page may get swapped out.
> And the fault on "invalidate I line" could not be properly handled
> causing the oops.

You have to be very careful when doing this kind of change - you need to
review the behaviour of previous ARMs to ensure that you don't throw the
CPU into an infinite loop when an "external abort on linefetch" occurs.

With older CPUs, an "external abort on linefetch" is most probably fatal
to the process and can never be recovered.

[PATCH] Handle instruction cache maintenance fault properly

[Kirill A. Shutemov]

On Mon, May 10, 2010 at 4:15 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Mon, May 10, 2010 at 04:07:57PM +0300, Kirill A. Shutemov wrote:
>> Between "clean D line..." and "invalidate I line" operations in
>> v7_coherent_user_range(), the memory page may get swapped out.
>> And the fault on "invalidate I line" could not be properly handled
>> causing the oops.
>
> You have to be very careful when doing this kind of change - you need to
> review the behaviour of previous ARMs to ensure that you don't throw the
> CPU into an infinite loop when an "external abort on linefetch" occurs.
>
> With older CPUs, an "external abort on linefetch" is most probably fatal
> to the process and can never be recovered.

It looks like cache maintenance fault was introduced in ARMv6.

So, what is the right way to fix it? Something like:

#if __LINUX_ARM_ARCH__ < 6
        { do_bad,               SIGBUS,  0,             "external
abort on linefetch"      },
#else
        { do_translation_fault, SIGSEGV, SEGV_MAPERR,   "I-cache
maintenance fault"        },
#endif

Re: [PATCH] Handle instruction cache maintenance fault properly

[Kirill A. Shutemov]

On Mon, May 10, 2010 at 4:15 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Mon, May 10, 2010 at 04:07:57PM +0300, Kirill A. Shutemov wrote:
>> Between "clean D line..." and "invalidate I line" operations in
>> v7_coherent_user_range(), the memory page may get swapped out.
>> And the fault on "invalidate I line" could not be properly handled
>> causing the oops.
>
> You have to be very careful when doing this kind of change - you need to
> review the behaviour of previous ARMs to ensure that you don't throw the
> CPU into an infinite loop when an "external abort on linefetch" occurs.
>
> With older CPUs, an "external abort on linefetch" is most probably fatal
> to the process and can never be recovered.

It looks like cache maintenance fault was introduced in ARMv6.

So, what is the right way to fix it? Something like:

#if __LINUX_ARM_ARCH__ < 6
        { do_bad,               SIGBUS,  0,             "external
abort on linefetch"      },
#else
        { do_translation_fault, SIGSEGV, SEGV_MAPERR,   "I-cache
maintenance fault"        },
#endif

[PATCH] Handle instruction cache maintenance fault properly

[Valdis.Kletnieks at vt.edu]

On Mon, 10 May 2010 16:34:57 +0300, "Kirill A. Shutemov" said:

> It looks like cache maintenance fault was introduced in ARMv6.
> 
> So, what is the right way to fix it? Something like:
> 
> #if __LINUX_ARM_ARCH__ < 6
>         { do_bad,               SIGBUS,  0,             "external

This would need to be a runtime test, no?  Or does LINUX_ARM_ARCH not allow
it to run on other arch levels? (i.e. can an ARM kernel boot for v5 and v6?)
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Re: [PATCH] Handle instruction cache maintenance fault properly

[Valdis.Kletnieks]

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On Mon, 10 May 2010 16:34:57 +0300, "Kirill A. Shutemov" said:

> It looks like cache maintenance fault was introduced in ARMv6.
> 
> So, what is the right way to fix it? Something like:
> 
> #if __LINUX_ARM_ARCH__ < 6
>         { do_bad,               SIGBUS,  0,             "external

This would need to be a runtime test, no?  Or does LINUX_ARM_ARCH not allow
it to run on other arch levels? (i.e. can an ARM kernel boot for v5 and v6?)

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[PATCH] Handle instruction cache maintenance fault properly

[Catalin Marinas]

On Mon, 2010-05-10 at 15:52 +0100, Valdis.Kletnieks at vt.edu wrote:
> On Mon, 10 May 2010 16:34:57 +0300, "Kirill A. Shutemov" said:
> 
> > It looks like cache maintenance fault was introduced in ARMv6.
> > 
> > So, what is the right way to fix it? Something like:
> > 
> > #if __LINUX_ARM_ARCH__ < 6
> >         { do_bad,               SIGBUS,  0,             "external
> 
> This would need to be a runtime test, no?  Or does LINUX_ARM_ARCH not allow
> it to run on other arch levels? (i.e. can an ARM kernel boot for v5 and v6?)

v6 and v7 probably but I doubt v5 and v6 would work. There are other
#ifdefs in arch/arm/include/asm/system.h like barriers.

-- 
Catalin

Re: [PATCH] Handle instruction cache maintenance fault properly

[Catalin Marinas]

On Mon, 2010-05-10 at 15:52 +0100, Valdis.Kletnieks@vt.edu wrote:
> On Mon, 10 May 2010 16:34:57 +0300, "Kirill A. Shutemov" said:
> 
> > It looks like cache maintenance fault was introduced in ARMv6.
> > 
> > So, what is the right way to fix it? Something like:
> > 
> > #if __LINUX_ARM_ARCH__ < 6
> >         { do_bad,               SIGBUS,  0,             "external
> 
> This would need to be a runtime test, no?  Or does LINUX_ARM_ARCH not allow
> it to run on other arch levels? (i.e. can an ARM kernel boot for v5 and v6?)

v6 and v7 probably but I doubt v5 and v6 would work. There are other
#ifdefs in arch/arm/include/asm/system.h like barriers.

-- 
Catalin