From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
mike.leach@linaro.org, swboyd@chromium.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-arm-msm-owner@vger.kernel.org
Subject: Re: [PATCH] coresight: tmc: Read TMC mode only when TMC hw is enabled
Date: Tue, 14 Apr 2020 21:17:05 +0530 [thread overview]
Message-ID: <75ef334a7e2cc6d87deecadd12c74f59@codeaurora.org> (raw)
In-Reply-To: <20200413171418.GB28804@xps15>
Hi Mathieu,
On 2020-04-13 22:44, Mathieu Poirier wrote:
> On Mon, Apr 13, 2020 at 01:55:30PM +0530, Sai Prakash Ranjan wrote:
>> Hi Suzuki,
>>
>> On 2020-04-13 04:47, Suzuki K Poulose wrote:
>> > Hi Sai,
>> >
>> > On 04/09/2020 12:35 PM, Sai Prakash Ranjan wrote:
>> > > Reading TMC mode register in tmc_read_prepare_etb without
>> > > enabling the TMC hardware leads to async exceptions like
>> > > the one in the call trace below. This can happen if the
>> > > user tries to read the TMC etf data via device node without
>> > > setting up source and the sink first which enables the TMC
>> > > hardware in the path. So make sure that the TMC is enabled
>> > > before we try to read TMC data.
>> >
>> > So, one can trigger the same SError by simply :
>> >
>> > $ cat /sys/bus/coresight/device/tmc_etb0/mgmt/mode
>> >
>>
>> I do not see any SError when I run the above command.
>>
>> localhost ~ # cat /sys/bus/coresight/devices/tmc_etf0/mgmt/mode
>> 0x0
>>
>> And this is most likely due to
>>
>> commit cd9e3474bb793dc ("coresight: add PM runtime calls to
>> coresight_simple_func()")
>
> Ok, so this is related to power management (you can ignore my question
> in the
> previous email).
>
> Regarding function tmc_read_prepare_etb(), the best way to deal with
> this is
> probably make sure drvdata->mode != CS_MODE_DISABLED before reading
> TMC_MODE.
> If there is a buffer to read it will have been copied when the ETB was
> disabled
> and there won't be a need to access the HW.
>
This works as well, thanks.
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c
b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index d0cc3985b72a..7ffe05930984 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -596,6 +596,11 @@ int tmc_read_prepare_etb(struct tmc_drvdata
*drvdata)
goto out;
}
+ if (drvdata->mode == CS_MODE_DISABLED) {
+ ret = -EINVAL;
+ goto out;
+ }
+
/* There is no point in reading a TMC in HW FIFO mode */
mode = readl_relaxed(drvdata->base + TMC_MODE);
if (mode != TMC_MODE_CIRCULAR_BUFFER) {
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
WARNING: multiple messages have this Message-ID (diff)
From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
swboyd@chromium.org, linux-arm-msm-owner@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org
Subject: Re: [PATCH] coresight: tmc: Read TMC mode only when TMC hw is enabled
Date: Tue, 14 Apr 2020 21:17:05 +0530 [thread overview]
Message-ID: <75ef334a7e2cc6d87deecadd12c74f59@codeaurora.org> (raw)
In-Reply-To: <20200413171418.GB28804@xps15>
Hi Mathieu,
On 2020-04-13 22:44, Mathieu Poirier wrote:
> On Mon, Apr 13, 2020 at 01:55:30PM +0530, Sai Prakash Ranjan wrote:
>> Hi Suzuki,
>>
>> On 2020-04-13 04:47, Suzuki K Poulose wrote:
>> > Hi Sai,
>> >
>> > On 04/09/2020 12:35 PM, Sai Prakash Ranjan wrote:
>> > > Reading TMC mode register in tmc_read_prepare_etb without
>> > > enabling the TMC hardware leads to async exceptions like
>> > > the one in the call trace below. This can happen if the
>> > > user tries to read the TMC etf data via device node without
>> > > setting up source and the sink first which enables the TMC
>> > > hardware in the path. So make sure that the TMC is enabled
>> > > before we try to read TMC data.
>> >
>> > So, one can trigger the same SError by simply :
>> >
>> > $ cat /sys/bus/coresight/device/tmc_etb0/mgmt/mode
>> >
>>
>> I do not see any SError when I run the above command.
>>
>> localhost ~ # cat /sys/bus/coresight/devices/tmc_etf0/mgmt/mode
>> 0x0
>>
>> And this is most likely due to
>>
>> commit cd9e3474bb793dc ("coresight: add PM runtime calls to
>> coresight_simple_func()")
>
> Ok, so this is related to power management (you can ignore my question
> in the
> previous email).
>
> Regarding function tmc_read_prepare_etb(), the best way to deal with
> this is
> probably make sure drvdata->mode != CS_MODE_DISABLED before reading
> TMC_MODE.
> If there is a buffer to read it will have been copied when the ETB was
> disabled
> and there won't be a need to access the HW.
>
This works as well, thanks.
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c
b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index d0cc3985b72a..7ffe05930984 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -596,6 +596,11 @@ int tmc_read_prepare_etb(struct tmc_drvdata
*drvdata)
goto out;
}
+ if (drvdata->mode == CS_MODE_DISABLED) {
+ ret = -EINVAL;
+ goto out;
+ }
+
/* There is no point in reading a TMC in HW FIFO mode */
mode = readl_relaxed(drvdata->base + TMC_MODE);
if (mode != TMC_MODE_CIRCULAR_BUFFER) {
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-04-14 15:47 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-09 11:35 [PATCH] coresight: tmc: Read TMC mode only when TMC hw is enabled Sai Prakash Ranjan
2020-04-09 11:35 ` Sai Prakash Ranjan
2020-04-09 19:34 ` Stephen Boyd
2020-04-09 19:34 ` Stephen Boyd
2020-04-12 23:17 ` Suzuki K Poulose
2020-04-12 23:17 ` Suzuki K Poulose
2020-04-13 8:25 ` Sai Prakash Ranjan
2020-04-13 8:25 ` Sai Prakash Ranjan
2020-04-13 17:14 ` Mathieu Poirier
2020-04-13 17:14 ` Mathieu Poirier
2020-04-14 15:47 ` Sai Prakash Ranjan [this message]
2020-04-14 15:47 ` Sai Prakash Ranjan
2020-04-15 15:56 ` Mathieu Poirier
2020-04-15 15:56 ` Mathieu Poirier
2020-04-16 16:17 ` Sai Prakash Ranjan
2020-04-16 16:17 ` Sai Prakash Ranjan
2020-04-13 16:56 ` Mathieu Poirier
2020-04-13 16:56 ` Mathieu Poirier
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