[PATCH 0/2] Add MT8173 MMPLL change rate support

[PATCH 0/2] Add MT8173 MMPLL change rate support

[James Liao]

MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting, includes:

1. Add div-rate table for PLLs.
2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
3. Write postdiv and pcw settings at the same time.

James Liao (2):
  clk: mediatek: Fix PLL registers setting flow
  clk: mediatek: Add MT8173 MMPLL change rate support

 drivers/clk/mediatek/clk-mt8173.c | 24 +++++++++++++++++++++---
 drivers/clk/mediatek/clk-mtk.h    |  6 ++++++
 drivers/clk/mediatek/clk-pll.c    | 39 +++++++++++++++++++++++++++------------
 3 files changed, 54 insertions(+), 15 deletions(-)

--
1.8.1.1.dirty

[PATCH 0/2] Add MT8173 MMPLL change rate support

[James Liao]

MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting, includes:

1. Add div-rate table for PLLs.
2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
3. Write postdiv and pcw settings at the same time.

James Liao (2):
  clk: mediatek: Fix PLL registers setting flow
  clk: mediatek: Add MT8173 MMPLL change rate support

 drivers/clk/mediatek/clk-mt8173.c | 24 +++++++++++++++++++++---
 drivers/clk/mediatek/clk-mtk.h    |  6 ++++++
 drivers/clk/mediatek/clk-pll.c    | 39 +++++++++++++++++++++++++++------------
 3 files changed, 54 insertions(+), 15 deletions(-)

--
1.8.1.1.dirty

[PATCH 0/2] Add MT8173 MMPLL change rate support

[James Liao]

MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting, includes:

1. Add div-rate table for PLLs.
2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
3. Write postdiv and pcw settings at the same time.

James Liao (2):
  clk: mediatek: Fix PLL registers setting flow
  clk: mediatek: Add MT8173 MMPLL change rate support

 drivers/clk/mediatek/clk-mt8173.c | 24 +++++++++++++++++++++---
 drivers/clk/mediatek/clk-mtk.h    |  6 ++++++
 drivers/clk/mediatek/clk-pll.c    | 39 +++++++++++++++++++++++++++------------
 3 files changed, 54 insertions(+), 15 deletions(-)

--
1.8.1.1.dirty

[PATCH v2 1/2] clk: mediatek: Fix PLL registers setting flow

[James Liao]

Write postdiv and pcw settings at the same time for PLLs if postdiv
and pcw settings are on the same register.

This is need by PLLs such as MT8173 MMPLL and ARM*PLL.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
---
 drivers/clk/mediatek/clk-pll.c | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 44409e9..68af518 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -90,20 +90,23 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
 		int postdiv)
 {
-	u32 con1, pd, val;
+	u32 con1, val;
 	int pll_en;
 
-	/* set postdiv */
-	pd = readl(pll->pd_addr);
-	pd &= ~(POSTDIV_MASK << pll->data->pd_shift);
-	pd |= (ffs(postdiv) - 1) << pll->data->pd_shift;
-	writel(pd, pll->pd_addr);
-
 	pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
 
-	/* set pcw */
-	val = readl(pll->pcw_addr);
+	/* set postdiv */
+	val = readl(pll->pd_addr);
+	val &= ~(POSTDIV_MASK << pll->data->pd_shift);
+	val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
+
+	/* postdiv and pcw need to set at the same time if on same register */
+	if (pll->pd_addr != pll->pcw_addr) {
+		writel(val, pll->pd_addr);
+		val = readl(pll->pcw_addr);
+	}
 
+	/* set pcw */
 	val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
 			pll->data->pcw_shift);
 	val |= pcw << pll->data->pcw_shift;
-- 
1.8.1.1.dirty

[PATCH v2 1/2] clk: mediatek: Fix PLL registers setting flow

[James Liao]

Write postdiv and pcw settings at the same time for PLLs if postdiv
and pcw settings are on the same register.

This is need by PLLs such as MT8173 MMPLL and ARM*PLL.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
---
 drivers/clk/mediatek/clk-pll.c | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 44409e9..68af518 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -90,20 +90,23 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
 		int postdiv)
 {
-	u32 con1, pd, val;
+	u32 con1, val;
 	int pll_en;
 
-	/* set postdiv */
-	pd = readl(pll->pd_addr);
-	pd &= ~(POSTDIV_MASK << pll->data->pd_shift);
-	pd |= (ffs(postdiv) - 1) << pll->data->pd_shift;
-	writel(pd, pll->pd_addr);
-
 	pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
 
-	/* set pcw */
-	val = readl(pll->pcw_addr);
+	/* set postdiv */
+	val = readl(pll->pd_addr);
+	val &= ~(POSTDIV_MASK << pll->data->pd_shift);
+	val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
+
+	/* postdiv and pcw need to set at the same time if on same register */
+	if (pll->pd_addr != pll->pcw_addr) {
+		writel(val, pll->pd_addr);
+		val = readl(pll->pcw_addr);
+	}
 
+	/* set pcw */
 	val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
 			pll->data->pcw_shift);
 	val |= pcw << pll->data->pcw_shift;
-- 
1.8.1.1.dirty

[PATCH v2 1/2] clk: mediatek: Fix PLL registers setting flow

[James Liao]

Write postdiv and pcw settings at the same time for PLLs if postdiv
and pcw settings are on the same register.

This is need by PLLs such as MT8173 MMPLL and ARM*PLL.

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
---
 drivers/clk/mediatek/clk-pll.c | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 44409e9..68af518 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -90,20 +90,23 @@ static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
 static void mtk_pll_set_rate_regs(struct mtk_clk_pll *pll, u32 pcw,
 		int postdiv)
 {
-	u32 con1, pd, val;
+	u32 con1, val;
 	int pll_en;
 
-	/* set postdiv */
-	pd = readl(pll->pd_addr);
-	pd &= ~(POSTDIV_MASK << pll->data->pd_shift);
-	pd |= (ffs(postdiv) - 1) << pll->data->pd_shift;
-	writel(pd, pll->pd_addr);
-
 	pll_en = readl(pll->base_addr + REG_CON0) & CON0_BASE_EN;
 
-	/* set pcw */
-	val = readl(pll->pcw_addr);
+	/* set postdiv */
+	val = readl(pll->pd_addr);
+	val &= ~(POSTDIV_MASK << pll->data->pd_shift);
+	val |= (ffs(postdiv) - 1) << pll->data->pd_shift;
+
+	/* postdiv and pcw need to set at the same time if on same register */
+	if (pll->pd_addr != pll->pcw_addr) {
+		writel(val, pll->pd_addr);
+		val = readl(pll->pcw_addr);
+	}
 
+	/* set pcw */
 	val &= ~GENMASK(pll->data->pcw_shift + pll->data->pcwbits - 1,
 			pll->data->pcw_shift);
 	val |= pcw << pll->data->pcw_shift;
-- 
1.8.1.1.dirty

Re: [PATCH v2 1/2] clk: mediatek: Fix PLL registers setting flow

[Heiko Stübner]

Am Mittwoch, 8. Juli 2015, 16:37:45 schrieb James Liao:
> Write postdiv and pcw settings at the same time for PLLs if postdiv
> and pcw settings are on the same register.
> 
> This is need by PLLs such as MT8173 MMPLL and ARM*PLL.
> 
> Signed-off-by: James Liao <jamesjj.liao@mediatek.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

[PATCH v2 1/2] clk: mediatek: Fix PLL registers setting flow

[Heiko Stübner]

Am Mittwoch, 8. Juli 2015, 16:37:45 schrieb James Liao:
> Write postdiv and pcw settings at the same time for PLLs if postdiv
> and pcw settings are on the same register.
> 
> This is need by PLLs such as MT8173 MMPLL and ARM*PLL.
> 
> Signed-off-by: James Liao <jamesjj.liao@mediatek.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>

[PATCH v2 2/2] clk: mediatek: Add MT8173 MMPLL change rate support

[James Liao]

MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting, includes:

1. Add div-rate table for PLLs.
2. Increase the max ost divider setting from 3 (/8) to 4 (/16).

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
---
 drivers/clk/mediatek/clk-mt8173.c | 24 +++++++++++++++++++++---
 drivers/clk/mediatek/clk-mtk.h    |  6 ++++++
 drivers/clk/mediatek/clk-pll.c    | 18 +++++++++++++++---
 3 files changed, 42 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 357b080..e3101e6 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -779,8 +779,9 @@ CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 
 #define CON0_MT8173_RST_BAR	BIT(24)
 
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, \
-			_tuner_reg, _pcw_reg, _pcw_shift) { \
+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
+			_pcw_shift, _div_table) {			\
 		.id = _id,						\
 		.name = _name,						\
 		.reg = _reg,						\
@@ -795,14 +796,31 @@ CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 		.tuner_reg = _tuner_reg,				\
 		.pcw_reg = _pcw_reg,					\
 		.pcw_shift = _pcw_shift,				\
+		.div_table = _div_table,				\
 	}
 
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
+			_pcw_shift)					\
+		PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
+			NULL)
+
+static const struct mtk_pll_div_table mmpll_div_table[] = {
+	{ .div = 0, .freq = MT8173_PLL_FMAX },
+	{ .div = 1, .freq = 1000000000 },
+	{ .div = 2, .freq = 702000000 },
+	{ .div = 3, .freq = 253500000 },
+	{ .div = 4, .freq = 126750000 },
+	{ } /* sentinel */
+};
+
 static const struct mtk_pll_data plls[] = {
 	PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
 	PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
 	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0),
+	PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
 	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
 	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
 	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 61035b9..fa0c1fe 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -134,6 +134,11 @@ struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
 
 #define HAVE_RST_BAR	BIT(0)
 
+struct mtk_pll_div_table {
+	u32 div;
+	unsigned long freq;
+};
+
 struct mtk_pll_data {
 	int id;
 	const char *name;
@@ -150,6 +155,7 @@ struct mtk_pll_data {
 	int pcwbits;
 	uint32_t pcw_reg;
 	int pcw_shift;
+	const struct mtk_pll_div_table *div_table;
 };
 
 void __init mtk_clk_register_plls(struct device_node *node,
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 68af518..622e7b6 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -138,16 +138,28 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
 		u32 freq, u32 fin)
 {
 	unsigned long fmin = 1000 * MHZ;
+	const struct mtk_pll_div_table *div_table = pll->data->div_table;
 	u64 _pcw;
 	u32 val;
 
 	if (freq > pll->data->fmax)
 		freq = pll->data->fmax;
 
-	for (val = 0; val < 4; val++) {
+	if (div_table) {
+		if (freq > div_table[0].freq)
+			freq = div_table[0].freq;
+
+		for (val = 0; div_table[val + 1].freq != 0; val++) {
+			if (freq > div_table[val + 1].freq)
+				break;
+		}
 		*postdiv = 1 << val;
-		if (freq * *postdiv >= fmin)
-			break;
+	} else {
+		for (val = 0; val < 5; val++) {
+			*postdiv = 1 << val;
+			if ((u64)freq * *postdiv >= fmin)
+				break;
+		}
 	}
 
 	/* _pcw = freq * postdiv / fin * 2^pcwfbits */
-- 
1.8.1.1.dirty

[PATCH v2 2/2] clk: mediatek: Add MT8173 MMPLL change rate support

[James Liao]

MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting, includes:

1. Add div-rate table for PLLs.
2. Increase the max ost divider setting from 3 (/8) to 4 (/16).

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
---
 drivers/clk/mediatek/clk-mt8173.c | 24 +++++++++++++++++++++---
 drivers/clk/mediatek/clk-mtk.h    |  6 ++++++
 drivers/clk/mediatek/clk-pll.c    | 18 +++++++++++++++---
 3 files changed, 42 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 357b080..e3101e6 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -779,8 +779,9 @@ CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 
 #define CON0_MT8173_RST_BAR	BIT(24)
 
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, \
-			_tuner_reg, _pcw_reg, _pcw_shift) { \
+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
+			_pcw_shift, _div_table) {			\
 		.id = _id,						\
 		.name = _name,						\
 		.reg = _reg,						\
@@ -795,14 +796,31 @@ CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 		.tuner_reg = _tuner_reg,				\
 		.pcw_reg = _pcw_reg,					\
 		.pcw_shift = _pcw_shift,				\
+		.div_table = _div_table,				\
 	}
 
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
+			_pcw_shift)					\
+		PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
+			NULL)
+
+static const struct mtk_pll_div_table mmpll_div_table[] = {
+	{ .div = 0, .freq = MT8173_PLL_FMAX },
+	{ .div = 1, .freq = 1000000000 },
+	{ .div = 2, .freq = 702000000 },
+	{ .div = 3, .freq = 253500000 },
+	{ .div = 4, .freq = 126750000 },
+	{ } /* sentinel */
+};
+
 static const struct mtk_pll_data plls[] = {
 	PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
 	PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
 	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0),
+	PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
 	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
 	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
 	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 61035b9..fa0c1fe 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -134,6 +134,11 @@ struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
 
 #define HAVE_RST_BAR	BIT(0)
 
+struct mtk_pll_div_table {
+	u32 div;
+	unsigned long freq;
+};
+
 struct mtk_pll_data {
 	int id;
 	const char *name;
@@ -150,6 +155,7 @@ struct mtk_pll_data {
 	int pcwbits;
 	uint32_t pcw_reg;
 	int pcw_shift;
+	const struct mtk_pll_div_table *div_table;
 };
 
 void __init mtk_clk_register_plls(struct device_node *node,
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 68af518..622e7b6 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -138,16 +138,28 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
 		u32 freq, u32 fin)
 {
 	unsigned long fmin = 1000 * MHZ;
+	const struct mtk_pll_div_table *div_table = pll->data->div_table;
 	u64 _pcw;
 	u32 val;
 
 	if (freq > pll->data->fmax)
 		freq = pll->data->fmax;
 
-	for (val = 0; val < 4; val++) {
+	if (div_table) {
+		if (freq > div_table[0].freq)
+			freq = div_table[0].freq;
+
+		for (val = 0; div_table[val + 1].freq != 0; val++) {
+			if (freq > div_table[val + 1].freq)
+				break;
+		}
 		*postdiv = 1 << val;
-		if (freq * *postdiv >= fmin)
-			break;
+	} else {
+		for (val = 0; val < 5; val++) {
+			*postdiv = 1 << val;
+			if ((u64)freq * *postdiv >= fmin)
+				break;
+		}
 	}
 
 	/* _pcw = freq * postdiv / fin * 2^pcwfbits */
-- 
1.8.1.1.dirty

[PATCH v2 2/2] clk: mediatek: Add MT8173 MMPLL change rate support

[James Liao]

MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting, includes:

1. Add div-rate table for PLLs.
2. Increase the max ost divider setting from 3 (/8) to 4 (/16).

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
---
 drivers/clk/mediatek/clk-mt8173.c | 24 +++++++++++++++++++++---
 drivers/clk/mediatek/clk-mtk.h    |  6 ++++++
 drivers/clk/mediatek/clk-pll.c    | 18 +++++++++++++++---
 3 files changed, 42 insertions(+), 6 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 357b080..e3101e6 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -779,8 +779,9 @@ CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 
 #define CON0_MT8173_RST_BAR	BIT(24)
 
-#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, \
-			_tuner_reg, _pcw_reg, _pcw_shift) { \
+#define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
+			_pcw_shift, _div_table) {			\
 		.id = _id,						\
 		.name = _name,						\
 		.reg = _reg,						\
@@ -795,14 +796,31 @@ CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
 		.tuner_reg = _tuner_reg,				\
 		.pcw_reg = _pcw_reg,					\
 		.pcw_shift = _pcw_shift,				\
+		.div_table = _div_table,				\
 	}
 
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,	\
+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg,	\
+			_pcw_shift)					\
+		PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
+			_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
+			NULL)
+
+static const struct mtk_pll_div_table mmpll_div_table[] = {
+	{ .div = 0, .freq = MT8173_PLL_FMAX },
+	{ .div = 1, .freq = 1000000000 },
+	{ .div = 2, .freq = 702000000 },
+	{ .div = 3, .freq = 253500000 },
+	{ .div = 4, .freq = 126750000 },
+	{ } /* sentinel */
+};
+
 static const struct mtk_pll_data plls[] = {
 	PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
 	PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
 	PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
 	PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
-	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0),
+	PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
 	PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
 	PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
 	PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 61035b9..fa0c1fe 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -134,6 +134,11 @@ struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
 
 #define HAVE_RST_BAR	BIT(0)
 
+struct mtk_pll_div_table {
+	u32 div;
+	unsigned long freq;
+};
+
 struct mtk_pll_data {
 	int id;
 	const char *name;
@@ -150,6 +155,7 @@ struct mtk_pll_data {
 	int pcwbits;
 	uint32_t pcw_reg;
 	int pcw_shift;
+	const struct mtk_pll_div_table *div_table;
 };
 
 void __init mtk_clk_register_plls(struct device_node *node,
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 68af518..622e7b6 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -138,16 +138,28 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
 		u32 freq, u32 fin)
 {
 	unsigned long fmin = 1000 * MHZ;
+	const struct mtk_pll_div_table *div_table = pll->data->div_table;
 	u64 _pcw;
 	u32 val;
 
 	if (freq > pll->data->fmax)
 		freq = pll->data->fmax;
 
-	for (val = 0; val < 4; val++) {
+	if (div_table) {
+		if (freq > div_table[0].freq)
+			freq = div_table[0].freq;
+
+		for (val = 0; div_table[val + 1].freq != 0; val++) {
+			if (freq > div_table[val + 1].freq)
+				break;
+		}
 		*postdiv = 1 << val;
-		if (freq * *postdiv >= fmin)
-			break;
+	} else {
+		for (val = 0; val < 5; val++) {
+			*postdiv = 1 << val;
+			if ((u64)freq * *postdiv >= fmin)
+				break;
+		}
 	}
 
 	/* _pcw = freq * postdiv / fin * 2^pcwfbits */
-- 
1.8.1.1.dirty

Re: [PATCH v2 2/2] clk: mediatek: Add MT8173 MMPLL change rate support

[Stephen Boyd]

On 07/08/2015 01:37 AM, James Liao wrote:
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 68af518..622e7b6 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -138,16 +138,28 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
>  		u32 freq, u32 fin)
>  {
>  	unsigned long fmin = 1000 * MHZ;
> +	const struct mtk_pll_div_table *div_table = pll->data->div_table;
>  	u64 _pcw;
>  	u32 val;
>  
>  	if (freq > pll->data->fmax)
>  		freq = pll->data->fmax;
>  
> -	for (val = 0; val < 4; val++) {
> +	if (div_table) {
> +		if (freq > div_table[0].freq)
> +			freq = div_table[0].freq;
> +
> +		for (val = 0; div_table[val + 1].freq != 0; val++) {
> +			if (freq > div_table[val + 1].freq)
> +				break;
> +		}
>  		*postdiv = 1 << val;
> -		if (freq * *postdiv >= fmin)
> -			break;
> +	} else {
> +		for (val = 0; val < 5; val++) {
> +			*postdiv = 1 << val;
> +			if ((u64)freq * *postdiv >= fmin)
>

No mention of this cast in the commit text. Is this fixing a bug? If so,
please mention it and/or split this bug fix off of this patch.

-- 
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a Linux Foundation Collaborative Project

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Re: [PATCH v2 2/2] clk: mediatek: Add MT8173 MMPLL change rate support

[Stephen Boyd]

On 07/08/2015 01:37 AM, James Liao wrote:
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 68af518..622e7b6 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -138,16 +138,28 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
>  		u32 freq, u32 fin)
>  {
>  	unsigned long fmin = 1000 * MHZ;
> +	const struct mtk_pll_div_table *div_table = pll->data->div_table;
>  	u64 _pcw;
>  	u32 val;
>  
>  	if (freq > pll->data->fmax)
>  		freq = pll->data->fmax;
>  
> -	for (val = 0; val < 4; val++) {
> +	if (div_table) {
> +		if (freq > div_table[0].freq)
> +			freq = div_table[0].freq;
> +
> +		for (val = 0; div_table[val + 1].freq != 0; val++) {
> +			if (freq > div_table[val + 1].freq)
> +				break;
> +		}
>  		*postdiv = 1 << val;
> -		if (freq * *postdiv >= fmin)
> -			break;
> +	} else {
> +		for (val = 0; val < 5; val++) {
> +			*postdiv = 1 << val;
> +			if ((u64)freq * *postdiv >= fmin)
>

No mention of this cast in the commit text. Is this fixing a bug? If so,
please mention it and/or split this bug fix off of this patch.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v2 2/2] clk: mediatek: Add MT8173 MMPLL change rate support

[Stephen Boyd]

On 07/08/2015 01:37 AM, James Liao wrote:
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 68af518..622e7b6 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -138,16 +138,28 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
>  		u32 freq, u32 fin)
>  {
>  	unsigned long fmin = 1000 * MHZ;
> +	const struct mtk_pll_div_table *div_table = pll->data->div_table;
>  	u64 _pcw;
>  	u32 val;
>  
>  	if (freq > pll->data->fmax)
>  		freq = pll->data->fmax;
>  
> -	for (val = 0; val < 4; val++) {
> +	if (div_table) {
> +		if (freq > div_table[0].freq)
> +			freq = div_table[0].freq;
> +
> +		for (val = 0; div_table[val + 1].freq != 0; val++) {
> +			if (freq > div_table[val + 1].freq)
> +				break;
> +		}
>  		*postdiv = 1 << val;
> -		if (freq * *postdiv >= fmin)
> -			break;
> +	} else {
> +		for (val = 0; val < 5; val++) {
> +			*postdiv = 1 << val;
> +			if ((u64)freq * *postdiv >= fmin)
>

No mention of this cast in the commit text. Is this fixing a bug? If so,
please mention it and/or split this bug fix off of this patch.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v2 2/2] clk: mediatek: Add MT8173 MMPLL change rate support

[James Liao]

Hi Stephen,

On Wed, 2015-07-08 at 17:46 -0700, Stephen Boyd wrote:
> On 07/08/2015 01:37 AM, James Liao wrote:
> > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> > index 68af518..622e7b6 100644
> > --- a/drivers/clk/mediatek/clk-pll.c
> > +++ b/drivers/clk/mediatek/clk-pll.c
> > @@ -138,16 +138,28 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
> >  		u32 freq, u32 fin)
> >  {
> >  	unsigned long fmin = 1000 * MHZ;
> > +	const struct mtk_pll_div_table *div_table = pll->data->div_table;
> >  	u64 _pcw;
> >  	u32 val;
> >  
> >  	if (freq > pll->data->fmax)
> >  		freq = pll->data->fmax;
> >  
> > -	for (val = 0; val < 4; val++) {
> > +	if (div_table) {
> > +		if (freq > div_table[0].freq)
> > +			freq = div_table[0].freq;
> > +
> > +		for (val = 0; div_table[val + 1].freq != 0; val++) {
> > +			if (freq > div_table[val + 1].freq)
> > +				break;
> > +		}
> >  		*postdiv = 1 << val;
> > -		if (freq * *postdiv >= fmin)
> > -			break;
> > +	} else {
> > +		for (val = 0; val < 5; val++) {
> > +			*postdiv = 1 << val;
> > +			if ((u64)freq * *postdiv >= fmin)
> >
> 
> No mention of this cast in the commit text. Is this fixing a bug? If so,
> please mention it and/or split this bug fix off of this patch.
> 

Yes, this is a fix to avoid u32 overflow. I'll split it in next patch.


Best regards,

James


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Re: [PATCH v2 2/2] clk: mediatek: Add MT8173 MMPLL change rate support

[James Liao]

Hi Stephen,

On Wed, 2015-07-08 at 17:46 -0700, Stephen Boyd wrote:
> On 07/08/2015 01:37 AM, James Liao wrote:
> > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> > index 68af518..622e7b6 100644
> > --- a/drivers/clk/mediatek/clk-pll.c
> > +++ b/drivers/clk/mediatek/clk-pll.c
> > @@ -138,16 +138,28 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
> >  		u32 freq, u32 fin)
> >  {
> >  	unsigned long fmin = 1000 * MHZ;
> > +	const struct mtk_pll_div_table *div_table = pll->data->div_table;
> >  	u64 _pcw;
> >  	u32 val;
> >  
> >  	if (freq > pll->data->fmax)
> >  		freq = pll->data->fmax;
> >  
> > -	for (val = 0; val < 4; val++) {
> > +	if (div_table) {
> > +		if (freq > div_table[0].freq)
> > +			freq = div_table[0].freq;
> > +
> > +		for (val = 0; div_table[val + 1].freq != 0; val++) {
> > +			if (freq > div_table[val + 1].freq)
> > +				break;
> > +		}
> >  		*postdiv = 1 << val;
> > -		if (freq * *postdiv >= fmin)
> > -			break;
> > +	} else {
> > +		for (val = 0; val < 5; val++) {
> > +			*postdiv = 1 << val;
> > +			if ((u64)freq * *postdiv >= fmin)
> >
> 
> No mention of this cast in the commit text. Is this fixing a bug? If so,
> please mention it and/or split this bug fix off of this patch.
> 

Yes, this is a fix to avoid u32 overflow. I'll split it in next patch.


Best regards,

James

[PATCH v2 2/2] clk: mediatek: Add MT8173 MMPLL change rate support

[James Liao]

Hi Stephen,

On Wed, 2015-07-08 at 17:46 -0700, Stephen Boyd wrote:
> On 07/08/2015 01:37 AM, James Liao wrote:
> > diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> > index 68af518..622e7b6 100644
> > --- a/drivers/clk/mediatek/clk-pll.c
> > +++ b/drivers/clk/mediatek/clk-pll.c
> > @@ -138,16 +138,28 @@ static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
> >  		u32 freq, u32 fin)
> >  {
> >  	unsigned long fmin = 1000 * MHZ;
> > +	const struct mtk_pll_div_table *div_table = pll->data->div_table;
> >  	u64 _pcw;
> >  	u32 val;
> >  
> >  	if (freq > pll->data->fmax)
> >  		freq = pll->data->fmax;
> >  
> > -	for (val = 0; val < 4; val++) {
> > +	if (div_table) {
> > +		if (freq > div_table[0].freq)
> > +			freq = div_table[0].freq;
> > +
> > +		for (val = 0; div_table[val + 1].freq != 0; val++) {
> > +			if (freq > div_table[val + 1].freq)
> > +				break;
> > +		}
> >  		*postdiv = 1 << val;
> > -		if (freq * *postdiv >= fmin)
> > -			break;
> > +	} else {
> > +		for (val = 0; val < 5; val++) {
> > +			*postdiv = 1 << val;
> > +			if ((u64)freq * *postdiv >= fmin)
> >
> 
> No mention of this cast in the commit text. Is this fixing a bug? If so,
> please mention it and/or split this bug fix off of this patch.
> 

Yes, this is a fix to avoid u32 overflow. I'll split it in next patch.


Best regards,

James

Re: [PATCH 0/2] Add MT8173 MMPLL change rate support

[James Liao]

Hi all,

The cover letter's title should be "[PATCH v2 0/2] ..."

changes since v1:
- Add a separated patch for mtk_pll_set_rate_regs().
- Use a structure array to describe a div_table.
- Limit max frequency to div_table[0].
- Minor changes such as static and comments.


Best regards,

James

On Wed, 2015-07-08 at 16:37 +0800, James Liao wrote:
> MT8173 MMPLL frequency settings are different from common PLLs.
> It needs different post divider settings for some ranges of frequency.
> This patch add support for MT8173 MMPLL frequency setting, includes:
> 
> 1. Add div-rate table for PLLs.
> 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> 3. Write postdiv and pcw settings at the same time.
> 
> James Liao (2):
>   clk: mediatek: Fix PLL registers setting flow
>   clk: mediatek: Add MT8173 MMPLL change rate support
> 
>  drivers/clk/mediatek/clk-mt8173.c | 24 +++++++++++++++++++++---
>  drivers/clk/mediatek/clk-mtk.h    |  6 ++++++
>  drivers/clk/mediatek/clk-pll.c    | 39 +++++++++++++++++++++++++++------------
>  3 files changed, 54 insertions(+), 15 deletions(-)
> 
> --
> 1.8.1.1.dirty
> 
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek


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Re: [PATCH 0/2] Add MT8173 MMPLL change rate support

[James Liao]

Hi all,

The cover letter's title should be "[PATCH v2 0/2] ..."

changes since v1:
- Add a separated patch for mtk_pll_set_rate_regs().
- Use a structure array to describe a div_table.
- Limit max frequency to div_table[0].
- Minor changes such as static and comments.


Best regards,

James

On Wed, 2015-07-08 at 16:37 +0800, James Liao wrote:
> MT8173 MMPLL frequency settings are different from common PLLs.
> It needs different post divider settings for some ranges of frequency.
> This patch add support for MT8173 MMPLL frequency setting, includes:
> 
> 1. Add div-rate table for PLLs.
> 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> 3. Write postdiv and pcw settings at the same time.
> 
> James Liao (2):
>   clk: mediatek: Fix PLL registers setting flow
>   clk: mediatek: Add MT8173 MMPLL change rate support
> 
>  drivers/clk/mediatek/clk-mt8173.c | 24 +++++++++++++++++++++---
>  drivers/clk/mediatek/clk-mtk.h    |  6 ++++++
>  drivers/clk/mediatek/clk-pll.c    | 39 +++++++++++++++++++++++++++------------
>  3 files changed, 54 insertions(+), 15 deletions(-)
> 
> --
> 1.8.1.1.dirty
> 
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH 0/2] Add MT8173 MMPLL change rate support

[James Liao]

Hi all,

The cover letter's title should be "[PATCH v2 0/2] ..."

changes since v1:
- Add a separated patch for mtk_pll_set_rate_regs().
- Use a structure array to describe a div_table.
- Limit max frequency to div_table[0].
- Minor changes such as static and comments.


Best regards,

James

On Wed, 2015-07-08 at 16:37 +0800, James Liao wrote:
> MT8173 MMPLL frequency settings are different from common PLLs.
> It needs different post divider settings for some ranges of frequency.
> This patch add support for MT8173 MMPLL frequency setting, includes:
> 
> 1. Add div-rate table for PLLs.
> 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> 3. Write postdiv and pcw settings at the same time.
> 
> James Liao (2):
>   clk: mediatek: Fix PLL registers setting flow
>   clk: mediatek: Add MT8173 MMPLL change rate support
> 
>  drivers/clk/mediatek/clk-mt8173.c | 24 +++++++++++++++++++++---
>  drivers/clk/mediatek/clk-mtk.h    |  6 ++++++
>  drivers/clk/mediatek/clk-pll.c    | 39 +++++++++++++++++++++++++++------------
>  3 files changed, 54 insertions(+), 15 deletions(-)
> 
> --
> 1.8.1.1.dirty
> 
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

Re: [PATCH 0/2] Add MT8173 MMPLL change rate support

[Stephen Boyd]

On 07/08/2015 01:37 AM, James Liao wrote:
> MT8173 MMPLL frequency settings are different from common PLLs.
> It needs different post divider settings for some ranges of frequency.
> This patch add support for MT8173 MMPLL frequency setting, includes:
>
> 1. Add div-rate table for PLLs.
> 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> 3. Write postdiv and pcw settings at the same time.
>
> James Liao (2):
>   clk: mediatek: Fix PLL registers setting flow
>   clk: mediatek: Add MT8173 MMPLL change rate support
>

Are these fixing regressions in 4.2-rc1? I don't see any "Fixes:" tag so
it's not clear and makes me want to defer these until v4.3. Furthermore,
the subject starts with "Add" so it sounds like a new feature.

-- 
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a Linux Foundation Collaborative Project

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Re: [PATCH 0/2] Add MT8173 MMPLL change rate support

[Stephen Boyd]

On 07/08/2015 01:37 AM, James Liao wrote:
> MT8173 MMPLL frequency settings are different from common PLLs.
> It needs different post divider settings for some ranges of frequency.
> This patch add support for MT8173 MMPLL frequency setting, includes:
>
> 1. Add div-rate table for PLLs.
> 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> 3. Write postdiv and pcw settings at the same time.
>
> James Liao (2):
>   clk: mediatek: Fix PLL registers setting flow
>   clk: mediatek: Add MT8173 MMPLL change rate support
>

Are these fixing regressions in 4.2-rc1? I don't see any "Fixes:" tag so
it's not clear and makes me want to defer these until v4.3. Furthermore,
the subject starts with "Add" so it sounds like a new feature.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 0/2] Add MT8173 MMPLL change rate support

[Stephen Boyd]

On 07/08/2015 01:37 AM, James Liao wrote:
> MT8173 MMPLL frequency settings are different from common PLLs.
> It needs different post divider settings for some ranges of frequency.
> This patch add support for MT8173 MMPLL frequency setting, includes:
>
> 1. Add div-rate table for PLLs.
> 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> 3. Write postdiv and pcw settings at the same time.
>
> James Liao (2):
>   clk: mediatek: Fix PLL registers setting flow
>   clk: mediatek: Add MT8173 MMPLL change rate support
>

Are these fixing regressions in 4.2-rc1? I don't see any "Fixes:" tag so
it's not clear and makes me want to defer these until v4.3. Furthermore,
the subject starts with "Add" so it sounds like a new feature.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 0/2] Add MT8173 MMPLL change rate support

[James Liao]

Hi Stephen,

On Wed, 2015-07-08 at 17:44 -0700, Stephen Boyd wrote:
> On 07/08/2015 01:37 AM, James Liao wrote:
> > MT8173 MMPLL frequency settings are different from common PLLs.
> > It needs different post divider settings for some ranges of frequency.
> > This patch add support for MT8173 MMPLL frequency setting, includes:
> >
> > 1. Add div-rate table for PLLs.
> > 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> > 3. Write postdiv and pcw settings at the same time.
> >
> > James Liao (2):
> >   clk: mediatek: Fix PLL registers setting flow
> >   clk: mediatek: Add MT8173 MMPLL change rate support
> >
> 
> Are these fixing regressions in 4.2-rc1? I don't see any "Fixes:" tag so
> it's not clear and makes me want to defer these until v4.3. Furthermore,
> the subject starts with "Add" so it sounds like a new feature.

This patchset is based on 4.1-rc1 but it had been tested on 4.2-rc1.
I'll send a new patch which based on 4.2-rc1.

This patchset contains some general PLL fixes and MMPLL set rate
support. We can say the last one is also a fix because changing some
specific rate on MMPLL may fail in current implementation.


Best regards,

James

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Re: [PATCH 0/2] Add MT8173 MMPLL change rate support

[James Liao]

Hi Stephen,

On Wed, 2015-07-08 at 17:44 -0700, Stephen Boyd wrote:
> On 07/08/2015 01:37 AM, James Liao wrote:
> > MT8173 MMPLL frequency settings are different from common PLLs.
> > It needs different post divider settings for some ranges of frequency.
> > This patch add support for MT8173 MMPLL frequency setting, includes:
> >
> > 1. Add div-rate table for PLLs.
> > 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> > 3. Write postdiv and pcw settings at the same time.
> >
> > James Liao (2):
> >   clk: mediatek: Fix PLL registers setting flow
> >   clk: mediatek: Add MT8173 MMPLL change rate support
> >
> 
> Are these fixing regressions in 4.2-rc1? I don't see any "Fixes:" tag so
> it's not clear and makes me want to defer these until v4.3. Furthermore,
> the subject starts with "Add" so it sounds like a new feature.

This patchset is based on 4.1-rc1 but it had been tested on 4.2-rc1.
I'll send a new patch which based on 4.2-rc1.

This patchset contains some general PLL fixes and MMPLL set rate
support. We can say the last one is also a fix because changing some
specific rate on MMPLL may fail in current implementation.


Best regards,

James

[PATCH 0/2] Add MT8173 MMPLL change rate support

[James Liao]

Hi Stephen,

On Wed, 2015-07-08 at 17:44 -0700, Stephen Boyd wrote:
> On 07/08/2015 01:37 AM, James Liao wrote:
> > MT8173 MMPLL frequency settings are different from common PLLs.
> > It needs different post divider settings for some ranges of frequency.
> > This patch add support for MT8173 MMPLL frequency setting, includes:
> >
> > 1. Add div-rate table for PLLs.
> > 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> > 3. Write postdiv and pcw settings at the same time.
> >
> > James Liao (2):
> >   clk: mediatek: Fix PLL registers setting flow
> >   clk: mediatek: Add MT8173 MMPLL change rate support
> >
> 
> Are these fixing regressions in 4.2-rc1? I don't see any "Fixes:" tag so
> it's not clear and makes me want to defer these until v4.3. Furthermore,
> the subject starts with "Add" so it sounds like a new feature.

This patchset is based on 4.1-rc1 but it had been tested on 4.2-rc1.
I'll send a new patch which based on 4.2-rc1.

This patchset contains some general PLL fixes and MMPLL set rate
support. We can say the last one is also a fix because changing some
specific rate on MMPLL may fail in current implementation.


Best regards,

James

Re: [PATCH 0/2] Add MT8173 MMPLL change rate support

[Stephen Boyd]

On 07/10, James Liao wrote:
> Hi Stephen,
> 
> On Wed, 2015-07-08 at 17:44 -0700, Stephen Boyd wrote:
> > On 07/08/2015 01:37 AM, James Liao wrote:
> > > MT8173 MMPLL frequency settings are different from common PLLs.
> > > It needs different post divider settings for some ranges of frequency.
> > > This patch add support for MT8173 MMPLL frequency setting, includes:
> > >
> > > 1. Add div-rate table for PLLs.
> > > 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> > > 3. Write postdiv and pcw settings at the same time.
> > >
> > > James Liao (2):
> > >   clk: mediatek: Fix PLL registers setting flow
> > >   clk: mediatek: Add MT8173 MMPLL change rate support
> > >
> > 
> > Are these fixing regressions in 4.2-rc1? I don't see any "Fixes:" tag so
> > it's not clear and makes me want to defer these until v4.3. Furthermore,
> > the subject starts with "Add" so it sounds like a new feature.
> 
> This patchset is based on 4.1-rc1 but it had been tested on 4.2-rc1.
> I'll send a new patch which based on 4.2-rc1.
> 
> This patchset contains some general PLL fixes and MMPLL set rate
> support. We can say the last one is also a fix because changing some
> specific rate on MMPLL may fail in current implementation.
> 
> 

I'm seriously confused. The files these patches touch were never
in v4.1, so they can't be based on v4.1-rc1 unless you're saying
they were on top of clk-next when it was based on 4.1-rc1?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH 0/2] Add MT8173 MMPLL change rate support

[Stephen Boyd]

On 07/10, James Liao wrote:
> Hi Stephen,
> 
> On Wed, 2015-07-08 at 17:44 -0700, Stephen Boyd wrote:
> > On 07/08/2015 01:37 AM, James Liao wrote:
> > > MT8173 MMPLL frequency settings are different from common PLLs.
> > > It needs different post divider settings for some ranges of frequency.
> > > This patch add support for MT8173 MMPLL frequency setting, includes:
> > >
> > > 1. Add div-rate table for PLLs.
> > > 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> > > 3. Write postdiv and pcw settings at the same time.
> > >
> > > James Liao (2):
> > >   clk: mediatek: Fix PLL registers setting flow
> > >   clk: mediatek: Add MT8173 MMPLL change rate support
> > >
> > 
> > Are these fixing regressions in 4.2-rc1? I don't see any "Fixes:" tag so
> > it's not clear and makes me want to defer these until v4.3. Furthermore,
> > the subject starts with "Add" so it sounds like a new feature.
> 
> This patchset is based on 4.1-rc1 but it had been tested on 4.2-rc1.
> I'll send a new patch which based on 4.2-rc1.
> 
> This patchset contains some general PLL fixes and MMPLL set rate
> support. We can say the last one is also a fix because changing some
> specific rate on MMPLL may fail in current implementation.
> 
> 

I'm seriously confused. The files these patches touch were never
in v4.1, so they can't be based on v4.1-rc1 unless you're saying
they were on top of clk-next when it was based on 4.1-rc1?

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH 0/2] Add MT8173 MMPLL change rate support

[James Liao]

Hi Stephen,

On Tue, 2015-07-14 at 15:13 -0700, Stephen Boyd wrote:
> On 07/10, James Liao wrote:
> > On Wed, 2015-07-08 at 17:44 -0700, Stephen Boyd wrote:
> > > On 07/08/2015 01:37 AM, James Liao wrote:
> > > > MT8173 MMPLL frequency settings are different from common PLLs.
> > > > It needs different post divider settings for some ranges of frequency.
> > > > This patch add support for MT8173 MMPLL frequency setting, includes:
> > > >
> > > > 1. Add div-rate table for PLLs.
> > > > 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> > > > 3. Write postdiv and pcw settings at the same time.
> > > >
> > > > James Liao (2):
> > > >   clk: mediatek: Fix PLL registers setting flow
> > > >   clk: mediatek: Add MT8173 MMPLL change rate support
> > > >
> > > 
> > > Are these fixing regressions in 4.2-rc1? I don't see any "Fixes:" tag so
> > > it's not clear and makes me want to defer these until v4.3. Furthermore,
> > > the subject starts with "Add" so it sounds like a new feature.
> > 
> > This patchset is based on 4.1-rc1 but it had been tested on 4.2-rc1.
> > I'll send a new patch which based on 4.2-rc1.
> > 
> > This patchset contains some general PLL fixes and MMPLL set rate
> > support. We can say the last one is also a fix because changing some
> > specific rate on MMPLL may fail in current implementation.
> > 
> > 
> 
> I'm seriously confused. The files these patches touch were never
> in v4.1, so they can't be based on v4.1-rc1 unless you're saying
> they were on top of clk-next when it was based on 4.1-rc1?
> 

This is an old patch which based on 4.1-rc1 and basic clocks support
[1].

Please refer to the newer patch [2] and ignore this one.


[1] https://lkml.org/lkml/2015/4/23/92
[2] https://lkml.org/lkml/2015/7/10/198


Best regards,

James

Re: [PATCH 0/2] Add MT8173 MMPLL change rate support

[James Liao]

Hi Stephen,

On Tue, 2015-07-14 at 15:13 -0700, Stephen Boyd wrote:
> On 07/10, James Liao wrote:
> > On Wed, 2015-07-08 at 17:44 -0700, Stephen Boyd wrote:
> > > On 07/08/2015 01:37 AM, James Liao wrote:
> > > > MT8173 MMPLL frequency settings are different from common PLLs.
> > > > It needs different post divider settings for some ranges of frequency.
> > > > This patch add support for MT8173 MMPLL frequency setting, includes:
> > > >
> > > > 1. Add div-rate table for PLLs.
> > > > 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> > > > 3. Write postdiv and pcw settings at the same time.
> > > >
> > > > James Liao (2):
> > > >   clk: mediatek: Fix PLL registers setting flow
> > > >   clk: mediatek: Add MT8173 MMPLL change rate support
> > > >
> > > 
> > > Are these fixing regressions in 4.2-rc1? I don't see any "Fixes:" tag so
> > > it's not clear and makes me want to defer these until v4.3. Furthermore,
> > > the subject starts with "Add" so it sounds like a new feature.
> > 
> > This patchset is based on 4.1-rc1 but it had been tested on 4.2-rc1.
> > I'll send a new patch which based on 4.2-rc1.
> > 
> > This patchset contains some general PLL fixes and MMPLL set rate
> > support. We can say the last one is also a fix because changing some
> > specific rate on MMPLL may fail in current implementation.
> > 
> > 
> 
> I'm seriously confused. The files these patches touch were never
> in v4.1, so they can't be based on v4.1-rc1 unless you're saying
> they were on top of clk-next when it was based on 4.1-rc1?
> 

This is an old patch which based on 4.1-rc1 and basic clocks support
[1].

Please refer to the newer patch [2] and ignore this one.


[1] https://lkml.org/lkml/2015/4/23/92
[2] https://lkml.org/lkml/2015/7/10/198


Best regards,

James

[PATCH 0/2] Add MT8173 MMPLL change rate support

[James Liao]

Hi Stephen,

On Tue, 2015-07-14 at 15:13 -0700, Stephen Boyd wrote:
> On 07/10, James Liao wrote:
> > On Wed, 2015-07-08 at 17:44 -0700, Stephen Boyd wrote:
> > > On 07/08/2015 01:37 AM, James Liao wrote:
> > > > MT8173 MMPLL frequency settings are different from common PLLs.
> > > > It needs different post divider settings for some ranges of frequency.
> > > > This patch add support for MT8173 MMPLL frequency setting, includes:
> > > >
> > > > 1. Add div-rate table for PLLs.
> > > > 2. Increase the max ost divider setting from 3 (/8) to 4 (/16).
> > > > 3. Write postdiv and pcw settings at the same time.
> > > >
> > > > James Liao (2):
> > > >   clk: mediatek: Fix PLL registers setting flow
> > > >   clk: mediatek: Add MT8173 MMPLL change rate support
> > > >
> > > 
> > > Are these fixing regressions in 4.2-rc1? I don't see any "Fixes:" tag so
> > > it's not clear and makes me want to defer these until v4.3. Furthermore,
> > > the subject starts with "Add" so it sounds like a new feature.
> > 
> > This patchset is based on 4.1-rc1 but it had been tested on 4.2-rc1.
> > I'll send a new patch which based on 4.2-rc1.
> > 
> > This patchset contains some general PLL fixes and MMPLL set rate
> > support. We can say the last one is also a fix because changing some
> > specific rate on MMPLL may fail in current implementation.
> > 
> > 
> 
> I'm seriously confused. The files these patches touch were never
> in v4.1, so they can't be based on v4.1-rc1 unless you're saying
> they were on top of clk-next when it was based on 4.1-rc1?
> 

This is an old patch which based on 4.1-rc1 and basic clocks support
[1].

Please refer to the newer patch [2] and ignore this one.


[1] https://lkml.org/lkml/2015/4/23/92
[2] https://lkml.org/lkml/2015/7/10/198


Best regards,

James