Re: [PATCH] mtd: spi-nor: Fix quad-enable for flashes with QER bit in SR1

From: Jon Hunter <jonathanh@nvidia.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>,
	Pratyush Yadav <pratyush@kernel.org>,
	Michael Walle <mwalle@kernel.org>,
	Takahiro Kuwano <takahiro.kuwano@infineon.com>,
	Richard Weinberger <richard@nod.at>,
	Vignesh Raghavendra <vigneshr@ti.com>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Steam Lin <STLin2@winbond.com>,
	linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] mtd: spi-nor: Fix quad-enable for flashes with QER bit in SR1
Date: Fri, 11 Sep 2026 11:33:09 +0100	[thread overview]
Message-ID: <79b104a2-a76d-415b-b98c-6833d8cd298f@nvidia.com> (raw)
In-Reply-To: <20260911-perso-fix-spi-nor-qe-mxic-v1-1-fd6d91416a2a@bootlin.com>

On 11/09/2026 09:55, Miquel Raynal wrote:
> Some flashes (eg. from Macronix) do set BFPT_DWORD15_QER_SR1_BIT6, which
> means they do not have an SR2 to read from/write to. The new generic QE
> helper was supposed to accommodate this situation but in the last version
> that got merged, parts of that specific handling has been moved to a
> more contained location, swp.c (which needed most of the extra code),
> yet the Macronix case has been forgotten about in that generic QE
> handling helper. Booting with such flashes will always fail probing.
> 
> Fix the situation by making sure we do not attempt to read SR2 if the QE
> bit is in SR1.
> 
> Reported-by: Jon Hunter <jonathanh@nvidia.com>
> Closes: https://lore.kernel.org/linux-mtd/178876719232.3543902.14451625037676421254.b4-ty@b4/T/#m5bc4ba6776436f2870ced0eb5789d229037ad840
> Fixes: 63489002d397 ("mtd: spi-nor: Refactor Read Status/Write Status support")
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
>   drivers/mtd/spi-nor/core.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index e2b6efafdd8d..ac909dfb9657 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -985,7 +985,10 @@ static int spi_nor_generic_quad_enable(struct spi_nor *nor)
>   	if (!qe_mask[0] && !qe_mask[1])
>   		return 0;
>   
> -	ret = spi_nor_read_sr1_and_sr2(nor, sr);
> +	if (qe_mask[0])
> +		ret = spi_nor_read_sr1(nor, sr);
> +	else
> +		ret = spi_nor_read_sr1_and_sr2(nor, sr);
>   	if (ret)
>   		return ret;

I know that there is still some discussion going on about this
patch, but FWIW this does fix the issue I was seeing.

Thanks
Jon

-- 
nvpublic

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