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From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: Peter Maydell <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v2 6/9] target/arm: GICv5 cpuif: Use arm_cpu_set_irq() to set IRQ/FIQ status
Date: Wed, 7 Oct 2026 15:20:29 +0200	[thread overview]
Message-ID: <79f974bd-dcda-42cf-be57-6360f796ab0d@oss.qualcomm.com> (raw)
In-Reply-To: <20260914160020.327787-7-peter.maydell@linaro.org>

On 14/9/26 18:00, Peter Maydell wrote:
> Currently the GICv5 cpu interface directly calls cpu_interrupt() and
> cpu_reset_interrupt() to raise and lower IRQ and FIQ.  This is almost
> but not exactly what we do for GICv2/GICv3 external GPIO IRQ/FIQ line
> changes.  Those are handled by arm_cpu_set_irq(), and as well as
> calling cpu_interrupt() or cpu_reset_interrupt() they also update
> env->irq_line_state.
> 
> For IRQ and FIQ it doesn't matter whether we set and clear the bits
> in irq_line_state, because nothing looks at them.  But for VIRQ and
> VFIQ it will matter, because VIRQ and VFIQ are the logical OR of the
> line state and some bits in HCR_EL2.  We're going to need to call
> arm_cpu_set_irq() for VIRQ and VFIQ; for consistency, handle IRQ and
> FIQ that way too.
> 
> Since arm_cpu_set_irq() is now a function called from other parts of
> the CPU code, we make its first argument a properly typed one, with a
> wrapper taking void* for when we need to use it as a
> qemu_irq_handler.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   target/arm/cpu.c             | 14 +++++++++++---
>   target/arm/internals.h       | 14 ++++++++++++++
>   target/arm/tcg/gicv5-cpuif.c | 35 ++++-------------------------------
>   3 files changed, 29 insertions(+), 34 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>


  reply	other threads:[~2026-10-07 13:21 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-14 16:00 [PATCH v2 0/9] hw/intc/arm_gicv5: Minor fixes and cleanups Peter Maydell
2026-09-14 16:00 ` [PATCH v2 1/9] hw/intc/arm_gicv5: Ignore low bits in IRS_IST_BASER.ADDR Peter Maydell
2026-10-21 14:51   ` Richard Henderson
2026-09-14 16:00 ` [PATCH v2 2/9] hw/intc/arm_gicv5: Ignore low bits in L1_ISTE.L2_ADDR Peter Maydell
2026-10-21 14:52   ` Richard Henderson
2026-09-14 16:00 ` [PATCH v2 3/9] hw/intc/arm_gicv5: Regularize spacing in config_readl() switch Peter Maydell
2026-10-21 14:52   ` Richard Henderson
2026-09-14 16:00 ` [PATCH v2 4/9] hw/intc/arm_gicv5: Use cached IRS_IST_BASER.VALID state Peter Maydell
2026-10-21 14:53   ` Richard Henderson
2026-09-14 16:00 ` [PATCH v2 5/9] hw/intc/arm_gicv5: Free memory in finalize Peter Maydell
2026-09-14 16:00 ` [PATCH v2 6/9] target/arm: GICv5 cpuif: Use arm_cpu_set_irq() to set IRQ/FIQ status Peter Maydell
2026-10-07 13:20   ` Philippe Mathieu-Daudé [this message]
2026-09-14 16:00 ` [PATCH v2 7/9] target/arm: Only allow GICv5 on CPUs without AArch32 at EL1..3 Peter Maydell
2026-09-14 16:00 ` [PATCH v2 8/9] hw/intc/arm_gicv5: Pass CPU index to CPU interface Peter Maydell
2026-09-21 12:17   ` Philippe Mathieu-Daudé
2026-09-14 16:00 ` [PATCH v2 9/9] hw/intc/arm_gicv5: Pass cpuidx rather than iaffid in gicv5_get_hppi() Peter Maydell
2026-09-21 12:17   ` Philippe Mathieu-Daudé
2026-10-07 12:53 ` [PATCH v2 0/9] hw/intc/arm_gicv5: Minor fixes and cleanups Peter Maydell

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