From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v2 3/9] hw/intc/arm_gicv5: Regularize spacing in config_readl() switch
Date: Wed, 21 Oct 2026 16:52:33 +0200 [thread overview]
Message-ID: <ea1d0163-5dfd-4f9c-93f7-ecee49c4fc7c@linaro.org> (raw)
In-Reply-To: <20260914160020.327787-4-peter.maydell@linaro.org>
On 9/14/26 18:00, Peter Maydell wrote:
> In this file we don't put blank lines between cases in switches,
> except that for the switch in config_readl() we've written it half
> with blank lines and half without. Delete the blank lines to make it
> consistent with itself and the rest of the file.
>
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> Reviewed-by: Philippe Mathieu-Daudé<philmd@oss.qualcomm.com>
> ---
> hw/intc/arm_gicv5.c | 15 ---------------
> 1 file changed, 15 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2026-10-21 14:52 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-14 16:00 [PATCH v2 0/9] hw/intc/arm_gicv5: Minor fixes and cleanups Peter Maydell
2026-09-14 16:00 ` [PATCH v2 1/9] hw/intc/arm_gicv5: Ignore low bits in IRS_IST_BASER.ADDR Peter Maydell
2026-10-21 14:51 ` Richard Henderson
2026-09-14 16:00 ` [PATCH v2 2/9] hw/intc/arm_gicv5: Ignore low bits in L1_ISTE.L2_ADDR Peter Maydell
2026-10-21 14:52 ` Richard Henderson
2026-09-14 16:00 ` [PATCH v2 3/9] hw/intc/arm_gicv5: Regularize spacing in config_readl() switch Peter Maydell
2026-10-21 14:52 ` Richard Henderson [this message]
2026-09-14 16:00 ` [PATCH v2 4/9] hw/intc/arm_gicv5: Use cached IRS_IST_BASER.VALID state Peter Maydell
2026-10-21 14:53 ` Richard Henderson
2026-09-14 16:00 ` [PATCH v2 5/9] hw/intc/arm_gicv5: Free memory in finalize Peter Maydell
2026-09-14 16:00 ` [PATCH v2 6/9] target/arm: GICv5 cpuif: Use arm_cpu_set_irq() to set IRQ/FIQ status Peter Maydell
2026-10-07 13:20 ` Philippe Mathieu-Daudé
2026-09-14 16:00 ` [PATCH v2 7/9] target/arm: Only allow GICv5 on CPUs without AArch32 at EL1..3 Peter Maydell
2026-09-14 16:00 ` [PATCH v2 8/9] hw/intc/arm_gicv5: Pass CPU index to CPU interface Peter Maydell
2026-09-21 12:17 ` Philippe Mathieu-Daudé
2026-09-14 16:00 ` [PATCH v2 9/9] hw/intc/arm_gicv5: Pass cpuidx rather than iaffid in gicv5_get_hppi() Peter Maydell
2026-09-21 12:17 ` Philippe Mathieu-Daudé
2026-10-07 12:53 ` [PATCH v2 0/9] hw/intc/arm_gicv5: Minor fixes and cleanups Peter Maydell
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