From: Marc Zyngier <maz@kernel.org>
To: Andrew Scull <ascull@google.com>
Cc: kvm@vger.kernel.org, Andre Przywara <andre.przywara@arm.com>,
Dave Martin <Dave.Martin@arm.com>,
George Cherian <gcherian@marvell.com>,
"Zengtao \(B\)" <prime.zeng@hisilicon.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 08/26] KVM: arm64: Use TTL hint in when invalidating stage-2 translations
Date: Wed, 27 May 2020 09:59:48 +0100 [thread overview]
Message-ID: <7a2a533088ecc77f2c5a473e2c1c3004@kernel.org> (raw)
In-Reply-To: <20200513090648.GA193035@google.com>
On 2020-05-13 10:06, Andrew Scull wrote:
> On Tue, May 12, 2020 at 01:04:31PM +0100, James Morse wrote:
>> Hi Andrew,
>>
>> On 07/05/2020 16:13, Andrew Scull wrote:
>> >> @@ -176,7 +177,7 @@ static void clear_stage2_pud_entry(struct kvm_s2_mmu *mmu, pud_t *pud, phys_addr
>> >> pmd_t *pmd_table __maybe_unused = stage2_pmd_offset(kvm, pud, 0);
>> >> VM_BUG_ON(stage2_pud_huge(kvm, *pud));
>> >> stage2_pud_clear(kvm, pud);
>> >> - kvm_tlb_flush_vmid_ipa(mmu, addr);
>> >> + kvm_tlb_flush_vmid_ipa(mmu, addr, S2_NO_LEVEL_HINT);
>> >> stage2_pmd_free(kvm, pmd_table);
>> >> put_page(virt_to_page(pud));
>> >> }
>> >> @@ -186,7 +187,7 @@ static void clear_stage2_pmd_entry(struct kvm_s2_mmu *mmu, pmd_t *pmd, phys_addr
>> >> pte_t *pte_table = pte_offset_kernel(pmd, 0);
>> >> VM_BUG_ON(pmd_thp_or_huge(*pmd));
>> >> pmd_clear(pmd);
>> >> - kvm_tlb_flush_vmid_ipa(mmu, addr);
>> >> + kvm_tlb_flush_vmid_ipa(mmu, addr, S2_NO_LEVEL_HINT);
>> >> free_page((unsigned long)pte_table);
>> >> put_page(virt_to_page(pmd));
>> >> }
>> >
>> > Going by the names, is it possible to give a better level hint for these
>> > cases?
>>
>> There is no leaf entry being invalidated here. After clearing the
>> range, we found we'd
>> emptied (and invalidated) a whole page of mappings:
>> | if (stage2_pmd_table_empty(kvm, start_pmd))
>> | clear_stage2_pud_entry(mmu, pud, start_addr);
>>
>> Now we want to remove the link to the empty page so we can free it. We
>> are changing the
>> structure of the tables, not what gets mapped.
>>
>> I think this is why we need the un-hinted behaviour, to invalidate
>> "any level of the
>> translation table walk required to translate the specified IPA".
>> Otherwise the hardware
>> can look for a leaf at the indicated level, find none, and do nothing.
>>
>>
>> This is sufficiently horrible, its possible I've got it completely
>> wrong! (does it make
>> sense?)
>
> Ok. `addr` is an IPA, that IPA is now omitted from the map so doesn't
> appear in any entry of the table, least of all a leaf entry. That makes
> sense.
>
> Is there a convention to distinguish IPA and PA similar to the
> distinction for VA or does kvmarm just use phys_addr_t all round?
>
> It seems like the TTL patches are failry self contained if it would be
> easier to serparate them out from these larger series?
They are. This whole series is a mix of unrelated patches anyway.
Their only goal is to make my life a bit easier in the distant
future.
I'll repost that anyway, as I have made some cosmetic changes.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Andrew Scull <ascull@google.com>
Cc: kvm@vger.kernel.org, Andre Przywara <andre.przywara@arm.com>,
Dave Martin <Dave.Martin@arm.com>,
George Cherian <gcherian@marvell.com>,
James Morse <james.morse@arm.com>,
"Zengtao \(B\)" <prime.zeng@hisilicon.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 08/26] KVM: arm64: Use TTL hint in when invalidating stage-2 translations
Date: Wed, 27 May 2020 09:59:48 +0100 [thread overview]
Message-ID: <7a2a533088ecc77f2c5a473e2c1c3004@kernel.org> (raw)
In-Reply-To: <20200513090648.GA193035@google.com>
On 2020-05-13 10:06, Andrew Scull wrote:
> On Tue, May 12, 2020 at 01:04:31PM +0100, James Morse wrote:
>> Hi Andrew,
>>
>> On 07/05/2020 16:13, Andrew Scull wrote:
>> >> @@ -176,7 +177,7 @@ static void clear_stage2_pud_entry(struct kvm_s2_mmu *mmu, pud_t *pud, phys_addr
>> >> pmd_t *pmd_table __maybe_unused = stage2_pmd_offset(kvm, pud, 0);
>> >> VM_BUG_ON(stage2_pud_huge(kvm, *pud));
>> >> stage2_pud_clear(kvm, pud);
>> >> - kvm_tlb_flush_vmid_ipa(mmu, addr);
>> >> + kvm_tlb_flush_vmid_ipa(mmu, addr, S2_NO_LEVEL_HINT);
>> >> stage2_pmd_free(kvm, pmd_table);
>> >> put_page(virt_to_page(pud));
>> >> }
>> >> @@ -186,7 +187,7 @@ static void clear_stage2_pmd_entry(struct kvm_s2_mmu *mmu, pmd_t *pmd, phys_addr
>> >> pte_t *pte_table = pte_offset_kernel(pmd, 0);
>> >> VM_BUG_ON(pmd_thp_or_huge(*pmd));
>> >> pmd_clear(pmd);
>> >> - kvm_tlb_flush_vmid_ipa(mmu, addr);
>> >> + kvm_tlb_flush_vmid_ipa(mmu, addr, S2_NO_LEVEL_HINT);
>> >> free_page((unsigned long)pte_table);
>> >> put_page(virt_to_page(pmd));
>> >> }
>> >
>> > Going by the names, is it possible to give a better level hint for these
>> > cases?
>>
>> There is no leaf entry being invalidated here. After clearing the
>> range, we found we'd
>> emptied (and invalidated) a whole page of mappings:
>> | if (stage2_pmd_table_empty(kvm, start_pmd))
>> | clear_stage2_pud_entry(mmu, pud, start_addr);
>>
>> Now we want to remove the link to the empty page so we can free it. We
>> are changing the
>> structure of the tables, not what gets mapped.
>>
>> I think this is why we need the un-hinted behaviour, to invalidate
>> "any level of the
>> translation table walk required to translate the specified IPA".
>> Otherwise the hardware
>> can look for a leaf at the indicated level, find none, and do nothing.
>>
>>
>> This is sufficiently horrible, its possible I've got it completely
>> wrong! (does it make
>> sense?)
>
> Ok. `addr` is an IPA, that IPA is now omitted from the map so doesn't
> appear in any entry of the table, least of all a leaf entry. That makes
> sense.
>
> Is there a convention to distinguish IPA and PA similar to the
> distinction for VA or does kvmarm just use phys_addr_t all round?
>
> It seems like the TTL patches are failry self contained if it would be
> easier to serparate them out from these larger series?
They are. This whole series is a mix of unrelated patches anyway.
Their only goal is to make my life a bit easier in the distant
future.
I'll repost that anyway, as I have made some cosmetic changes.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Andrew Scull <ascull@google.com>
Cc: James Morse <james.morse@arm.com>,
kvm@vger.kernel.org, Andre Przywara <andre.przywara@arm.com>,
kvmarm@lists.cs.columbia.edu,
George Cherian <gcherian@marvell.com>,
"Zengtao (B)" <prime.zeng@hisilicon.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>, Dave Martin <Dave.Martin@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 08/26] KVM: arm64: Use TTL hint in when invalidating stage-2 translations
Date: Wed, 27 May 2020 09:59:48 +0100 [thread overview]
Message-ID: <7a2a533088ecc77f2c5a473e2c1c3004@kernel.org> (raw)
In-Reply-To: <20200513090648.GA193035@google.com>
On 2020-05-13 10:06, Andrew Scull wrote:
> On Tue, May 12, 2020 at 01:04:31PM +0100, James Morse wrote:
>> Hi Andrew,
>>
>> On 07/05/2020 16:13, Andrew Scull wrote:
>> >> @@ -176,7 +177,7 @@ static void clear_stage2_pud_entry(struct kvm_s2_mmu *mmu, pud_t *pud, phys_addr
>> >> pmd_t *pmd_table __maybe_unused = stage2_pmd_offset(kvm, pud, 0);
>> >> VM_BUG_ON(stage2_pud_huge(kvm, *pud));
>> >> stage2_pud_clear(kvm, pud);
>> >> - kvm_tlb_flush_vmid_ipa(mmu, addr);
>> >> + kvm_tlb_flush_vmid_ipa(mmu, addr, S2_NO_LEVEL_HINT);
>> >> stage2_pmd_free(kvm, pmd_table);
>> >> put_page(virt_to_page(pud));
>> >> }
>> >> @@ -186,7 +187,7 @@ static void clear_stage2_pmd_entry(struct kvm_s2_mmu *mmu, pmd_t *pmd, phys_addr
>> >> pte_t *pte_table = pte_offset_kernel(pmd, 0);
>> >> VM_BUG_ON(pmd_thp_or_huge(*pmd));
>> >> pmd_clear(pmd);
>> >> - kvm_tlb_flush_vmid_ipa(mmu, addr);
>> >> + kvm_tlb_flush_vmid_ipa(mmu, addr, S2_NO_LEVEL_HINT);
>> >> free_page((unsigned long)pte_table);
>> >> put_page(virt_to_page(pmd));
>> >> }
>> >
>> > Going by the names, is it possible to give a better level hint for these
>> > cases?
>>
>> There is no leaf entry being invalidated here. After clearing the
>> range, we found we'd
>> emptied (and invalidated) a whole page of mappings:
>> | if (stage2_pmd_table_empty(kvm, start_pmd))
>> | clear_stage2_pud_entry(mmu, pud, start_addr);
>>
>> Now we want to remove the link to the empty page so we can free it. We
>> are changing the
>> structure of the tables, not what gets mapped.
>>
>> I think this is why we need the un-hinted behaviour, to invalidate
>> "any level of the
>> translation table walk required to translate the specified IPA".
>> Otherwise the hardware
>> can look for a leaf at the indicated level, find none, and do nothing.
>>
>>
>> This is sufficiently horrible, its possible I've got it completely
>> wrong! (does it make
>> sense?)
>
> Ok. `addr` is an IPA, that IPA is now omitted from the map so doesn't
> appear in any entry of the table, least of all a leaf entry. That makes
> sense.
>
> Is there a convention to distinguish IPA and PA similar to the
> distinction for VA or does kvmarm just use phys_addr_t all round?
>
> It seems like the TTL patches are failry self contained if it would be
> easier to serparate them out from these larger series?
They are. This whole series is a mix of unrelated patches anyway.
Their only goal is to make my life a bit easier in the distant
future.
I'll repost that anyway, as I have made some cosmetic changes.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2020-05-27 8:59 UTC|newest]
Thread overview: 234+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-22 12:00 [PATCH 00/26] KVM: arm64: Preliminary NV patches Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 01/26] KVM: arm64: Check advertised Stage-2 page size capability Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 13:40 ` Suzuki K Poulose
2020-04-22 13:40 ` Suzuki K Poulose
2020-04-22 13:40 ` Suzuki K Poulose
2020-04-22 14:07 ` Marc Zyngier
2020-04-22 14:07 ` Marc Zyngier
2020-04-22 14:07 ` Marc Zyngier
2020-04-22 14:14 ` Suzuki K Poulose
2020-04-22 14:14 ` Suzuki K Poulose
2020-04-22 14:14 ` Suzuki K Poulose
2020-05-07 11:42 ` Alexandru Elisei
2020-05-07 11:42 ` Alexandru Elisei
2020-05-07 11:42 ` Alexandru Elisei
2020-04-22 12:00 ` [PATCH 02/26] KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 13:51 ` Suzuki K Poulose
2020-04-22 13:51 ` Suzuki K Poulose
2020-04-22 13:51 ` Suzuki K Poulose
2020-04-22 13:59 ` Marc Zyngier
2020-04-22 13:59 ` Marc Zyngier
2020-04-22 13:59 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 03/26] KVM: arm64: Factor out stage 2 page table data from struct kvm Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-05 15:26 ` Andrew Scull
2020-05-05 15:26 ` Andrew Scull
2020-05-05 15:26 ` Andrew Scull
2020-05-05 16:32 ` Marc Zyngier
2020-05-05 16:32 ` Marc Zyngier
2020-05-05 16:32 ` Marc Zyngier
2020-05-05 17:23 ` Andrew Scull
2020-05-05 17:23 ` Andrew Scull
2020-05-05 17:23 ` Andrew Scull
2020-05-05 18:10 ` Marc Zyngier
2020-05-05 18:10 ` Marc Zyngier
2020-05-05 18:10 ` Marc Zyngier
2020-05-05 16:03 ` James Morse
2020-05-05 16:03 ` James Morse
2020-05-05 16:03 ` James Morse
2020-05-05 17:59 ` Marc Zyngier
2020-05-05 17:59 ` Marc Zyngier
2020-05-05 17:59 ` Marc Zyngier
2020-05-06 9:30 ` Marc Zyngier
2020-05-06 9:30 ` Marc Zyngier
2020-05-06 9:30 ` Marc Zyngier
2020-05-11 16:38 ` Alexandru Elisei
2020-05-11 16:38 ` Alexandru Elisei
2020-05-11 16:38 ` Alexandru Elisei
2020-05-12 11:17 ` James Morse
2020-05-12 11:17 ` James Morse
2020-05-12 11:17 ` James Morse
2020-05-12 15:47 ` Alexandru Elisei
2020-05-12 15:47 ` Alexandru Elisei
2020-05-12 15:47 ` Alexandru Elisei
2020-05-12 16:13 ` James Morse
2020-05-12 16:13 ` James Morse
2020-05-12 16:13 ` James Morse
2020-05-12 16:53 ` Alexandru Elisei
2020-05-12 16:53 ` Alexandru Elisei
2020-05-12 16:53 ` Alexandru Elisei
2020-05-27 8:41 ` Marc Zyngier
2020-05-27 8:41 ` Marc Zyngier
2020-05-27 8:41 ` Marc Zyngier
2020-05-27 8:45 ` Alexandru Elisei
2020-05-27 8:45 ` Alexandru Elisei
2020-05-27 8:45 ` Alexandru Elisei
2020-04-22 12:00 ` [PATCH 04/26] arm64: Detect the ARMv8.4 TTL feature Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-27 15:55 ` Suzuki K Poulose
2020-04-27 15:55 ` Suzuki K Poulose
2020-04-27 15:55 ` Suzuki K Poulose
2020-04-22 12:00 ` [PATCH 05/26] arm64: Document SW reserved PTE/PMD bits in Stage-2 descriptors Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-05 15:59 ` Andrew Scull
2020-05-05 15:59 ` Andrew Scull
2020-05-05 15:59 ` Andrew Scull
2020-05-06 9:39 ` Marc Zyngier
2020-05-06 9:39 ` Marc Zyngier
2020-05-06 9:39 ` Marc Zyngier
2020-05-06 10:11 ` Andrew Scull
2020-05-06 10:11 ` Andrew Scull
2020-05-06 10:11 ` Andrew Scull
2020-04-22 12:00 ` [PATCH 06/26] arm64: Add level-hinted TLB invalidation helper Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-05 17:16 ` Andrew Scull
2020-05-05 17:16 ` Andrew Scull
2020-05-05 17:16 ` Andrew Scull
2020-05-06 8:05 ` Marc Zyngier
2020-05-06 8:05 ` Marc Zyngier
2020-05-06 8:05 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 07/26] KVM: arm64: Add a level hint to __kvm_tlb_flush_vmid_ipa Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-07 15:08 ` Andrew Scull
2020-05-07 15:08 ` Andrew Scull
2020-05-07 15:08 ` Andrew Scull
2020-05-07 15:13 ` Marc Zyngier
2020-05-07 15:13 ` Marc Zyngier
2020-05-07 15:13 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 08/26] KVM: arm64: Use TTL hint in when invalidating stage-2 translations Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-07 15:13 ` Andrew Scull
2020-05-07 15:13 ` Andrew Scull
2020-05-07 15:13 ` Andrew Scull
2020-05-12 12:04 ` James Morse
2020-05-12 12:04 ` James Morse
2020-05-12 12:04 ` James Morse
2020-05-13 9:06 ` Andrew Scull
2020-05-13 9:06 ` Andrew Scull
2020-05-13 9:06 ` Andrew Scull
2020-05-27 8:59 ` Marc Zyngier [this message]
2020-05-27 8:59 ` Marc Zyngier
2020-05-27 8:59 ` Marc Zyngier
2020-05-12 17:26 ` James Morse
2020-05-12 17:26 ` James Morse
2020-05-12 17:26 ` James Morse
2020-04-22 12:00 ` [PATCH 09/26] KVM: arm64: vgic-v3: Take cpu_if pointer directly instead of vcpu Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-07 16:26 ` James Morse
2020-05-07 16:26 ` James Morse
2020-05-07 16:26 ` James Morse
2020-05-08 12:20 ` Marc Zyngier
2020-05-08 12:20 ` Marc Zyngier
2020-05-08 12:20 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 10/26] KVM: arm64: Refactor vcpu_{read,write}_sys_reg Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:28 ` James Morse
2020-05-26 16:28 ` James Morse
2020-05-26 16:28 ` James Morse
2020-05-27 10:04 ` Marc Zyngier
2020-05-27 10:04 ` Marc Zyngier
2020-05-27 10:04 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 11/26] KVM: arm64: Add missing reset handlers for PMU emulation Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-04-22 12:00 ` [PATCH 12/26] KVM: arm64: Move sysreg reset check to boot time Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 13/26] KVM: arm64: Introduce accessor for ctxt->sys_reg Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 14/26] KVM: arm64: hyp: Use ctxt_sys_reg/__vcpu_sys_reg instead of raw sys_regs access Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 15/26] KVM: arm64: sve: Use __vcpu_sys_reg() " Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 16/26] KVM: arm64: pauth: Use ctxt_sys_reg() " Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 17/26] KVM: arm64: debug: " Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 18/26] KVM: arm64: Don't use empty structures as CPU reset state Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-24 4:07 ` Zenghui Yu
2020-04-24 4:07 ` Zenghui Yu
2020-04-24 4:07 ` Zenghui Yu
2020-04-24 7:45 ` Marc Zyngier
2020-04-24 7:45 ` Marc Zyngier
2020-04-24 7:45 ` Marc Zyngier
2020-04-28 1:34 ` Zengtao (B)
2020-04-28 1:34 ` Zengtao (B)
2020-04-28 1:34 ` Zengtao (B)
2020-04-22 12:00 ` [PATCH 19/26] KVM: arm64: Make struct kvm_regs userspace-only Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-05-27 10:22 ` Marc Zyngier
2020-05-27 10:22 ` Marc Zyngier
2020-05-27 10:22 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 20/26] KVM: arm64: Move ELR_EL1 to the system register array Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-05-27 10:36 ` Marc Zyngier
2020-05-27 10:36 ` Marc Zyngier
2020-05-27 10:36 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 21/26] KVM: arm64: Move SP_EL1 " Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-05-26 16:29 ` James Morse
2020-04-22 12:00 ` [PATCH 22/26] KVM: arm64: Disintegrate SPSR array Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:30 ` James Morse
2020-05-26 16:30 ` James Morse
2020-05-26 16:30 ` James Morse
2020-04-22 12:00 ` [PATCH 23/26] KVM: arm64: Move SPSR_EL1 to the system register array Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-26 16:30 ` James Morse
2020-05-26 16:30 ` James Morse
2020-05-26 16:30 ` James Morse
2020-04-22 12:00 ` [PATCH 24/26] KVM: arm64: timers: Rename kvm_timer_sync_hwstate to kvm_timer_sync_user Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 25/26] KVM: arm64: timers: Move timer registers to the sys_regs file Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` [PATCH 26/26] KVM: arm64: Parametrize exception entry with a target EL Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-04-22 12:00 ` Marc Zyngier
2020-05-19 10:44 ` Mark Rutland
2020-05-19 10:44 ` Mark Rutland
2020-05-19 10:44 ` Mark Rutland
2020-05-27 9:34 ` Marc Zyngier
2020-05-27 9:34 ` Marc Zyngier
2020-05-27 9:34 ` Marc Zyngier
2020-05-27 14:41 ` Mark Rutland
2020-05-27 14:41 ` Mark Rutland
2020-05-27 14:41 ` Mark Rutland
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