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* [Intel-gfx] [PATCH v6 0/4] Apply Wa_16018031267 / Wa_16018063123
@ 2023-10-26 18:36 Andrzej Hajda
  2023-10-26 18:36 ` [Intel-gfx] [PATCH v6 1/4] drm/i915: Reserve some kernel space per vm Andrzej Hajda
                   ` (14 more replies)
  0 siblings, 15 replies; 25+ messages in thread
From: Andrzej Hajda @ 2023-10-26 18:36 UTC (permalink / raw)
  To: intel-gfx
  Cc: Jonathan Cavitt, Andrzej Hajda,
	20231026-gtt_size_fix-v1-2-882d0e0022ec, Chris Wilson, Nirmoy Das

Hi all,

This the series from Jonathan:
[PATCH v12 0/4] Apply Wa_16018031267 / Wa_16018063123
taken over by me.

This patchset requires IGT changes fixing handling gtt sizes
not being power of 2:
https://patchwork.freedesktop.org/series/125640/

Changes in this version are described in the patches, in short:
v2:
- use real memory as WABB destination,
- address CI compains - do not decrease vm.total,
- minor reordering.
v3:
- fixed typos,
- removed spare defs,
- added tags
v4:
- removed NULL PTE patch,
- separate selftest to separate patch,
- use BB only on BCS0
v5:
- fixed reserved memory allocation
v6:
- decresase vm->total by reserved size

Regards
Andrzej

Andrzej Hajda (1):
  drm/i915: Reserve some kernel space per vm

Jonathan Cavitt (3):
  drm/i915: Enable NULL PTE support for vm scratch
  drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
  drm/i915: Set copy engine arbitration for Wa_16018031267 /
    Wa_16018063123

.../drm/i915/gem/selftests/i915_gem_context.c |   6 ++
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c          |  41 +++++++
 drivers/gpu/drm/i915/gt/intel_engine_regs.h   |   6 ++
 drivers/gpu/drm/i915/gt/intel_gt.h            |   4 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h      |   2 +
 drivers/gpu/drm/i915/gt/intel_gtt.h           |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc.c           | 100 +++++++++++++++++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |   5 +
 drivers/gpu/drm/i915/gt/selftest_lrc.c        |  65 ++++++++----
 drivers/gpu/drm/i915/i915_drv.h               |   2 +
 drivers/gpu/drm/i915/i915_pci.c               |   2 +
 drivers/gpu/drm/i915/intel_device_info.h      |   1 +
 12 files changed, 215 insertions(+), 21 deletions(-)

Test-with: 20231026-gtt_size_fix-v1-2-882d0e0022ec@intel.com
---
- Link to v3: https://lore.kernel.org/r/20231023-wabb-v3-0-1a4fbc632440@intel.com
- Link to v4: https://lore.kernel.org/r/20231023-wabb-v4-0-f75dec962b7d@intel.com
- Link to v5: https://lore.kernel.org/r/20231025-wabb-v5-0-398e42309e9d@intel.com

---
Andrzej Hajda (3):
      drm/i915: Reserve some kernel space per vm
      drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
      drm/i915/gt: add selftest to exercise WABB

Jonathan Cavitt (1):
      drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123

 drivers/gpu/drm/i915/gt/gen8_ppgtt.c        |  43 ++++++++++++
 drivers/gpu/drm/i915/gt/intel_engine_regs.h |   6 ++
 drivers/gpu/drm/i915/gt/intel_gt.h          |   4 ++
 drivers/gpu/drm/i915/gt/intel_gtt.h         |   4 ++
 drivers/gpu/drm/i915/gt/intel_lrc.c         | 100 +++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c |   5 ++
 drivers/gpu/drm/i915/gt/selftest_lrc.c      |  65 +++++++++++++-----
 7 files changed, 206 insertions(+), 21 deletions(-)
---
base-commit: 201c8a7bd1f3f415920a2df4b8a8817e973f42fe
change-id: 20231020-wabb-bbe9324a69a8

Best regards,
-- 
Andrzej Hajda <andrzej.hajda@intel.com>


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v12 0/4] Apply Wa_16018031267 / Wa_16018063123
@ 2023-09-20 21:07 Jonathan Cavitt
  2023-09-22  3:12 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork
  0 siblings, 1 reply; 25+ messages in thread
From: Jonathan Cavitt @ 2023-09-20 21:07 UTC (permalink / raw)
  To: intel-gfx
  Cc: andi.shyti, chris.p.wilson, tomasz.mistat, jonathan.cavitt,
	rodrigo.vivi, gregory.f.germano, matthew.d.roper, nirmoy.das

Apply Wa_16018031267 / Wa_16018063123.  This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.

v2:
- Rename old platform check in second patch to match
  declaration in first patch.
- Refactor second patch name to match first patch.

v3:
- Move NEEDS_FASTCOLOR_BLT_WABB to intel_gt.h.
- Refactor NEEDS_FASTCOLOR_BLT_WABB to make it more
  streamlined to use.
- Stop dividing PAGE_SIZE by sizeof(u32) when computing
  ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.
- Reduce comment complexity.
- Fix several checkpatch warnings.

v4:
- Actually stop dividing PAGE_SIZE by sizeof(u32) when
  computing ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.

v5:
- Stop dividing PAGE_SIZE by sizeof(u32) in
  check_ring_start during lrc live selftest.

v6:
- Append MI_BATCH_BUFFER_END to end of all PER_CTX_BB
  command streams.
- No longer skip on empty, as command stream will never
  be empty (always contains at least MI_BATCH_BUFFER_END).
- No longer append MI_NOOP until cachline aligned (was a
  fragment from INDIRECT_CTX setup).

v7:
- Use 0x6b instead of 0 for color to maintain functionality.

v8:
- Revert v7.
- Add some reserved kernel space per vm to run the
  workaround on.

v9:
- Hide reserved kernel space per vm from userspace.

v10:
- Revert v7 properly.
- Test on updated IGT.

v11:
- Remove Test-with tag.
- Reserve two pages per vm for workaround.

v12:
- Use Null page for scratch page.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Tomasz Mistat <tomasz.mistat@intel.com>
CC: Gregory F Germano <gregory.f.germano@intel.com>
CC: Matt Roper <matthew.d.roper@intel.com>
CC: James Ausmus <james.ausmus@intel.com>
CC: Chris Wilson <chris.p.wilson@linux.intel.com>
CC: Andi Shyti <andi.shyti@intel.com>

Jonathan Cavitt (4):
  drm/i915: Enable NULL PTE support for vm scratch
  drm/i915: Reserve some kernel space per vm
  drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
  drm/i915: Set copy engine arbitration for Wa_16018031267 /
    Wa_16018063123

 .../drm/i915/gem/selftests/i915_gem_context.c |   6 ++
 drivers/gpu/drm/i915/gt/gen8_ppgtt.c          |  10 ++
 drivers/gpu/drm/i915/gt/intel_engine_regs.h   |   6 ++
 drivers/gpu/drm/i915/gt/intel_gt.h            |   4 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h      |   2 +
 drivers/gpu/drm/i915/gt/intel_gtt.h           |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc.c           | 100 +++++++++++++++++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c   |   5 +
 drivers/gpu/drm/i915/gt/selftest_lrc.c        |  65 ++++++++----
 drivers/gpu/drm/i915/i915_drv.h               |   2 +
 drivers/gpu/drm/i915/i915_pci.c               |   2 +
 drivers/gpu/drm/i915/intel_device_info.h      |   1 +
 12 files changed, 184 insertions(+), 21 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v10 0/3] Apply Wa_16018031267 / Wa_16018063123
@ 2023-09-19 17:16 Jonathan Cavitt
  2023-09-19 22:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork
  0 siblings, 1 reply; 25+ messages in thread
From: Jonathan Cavitt @ 2023-09-19 17:16 UTC (permalink / raw)
  To: intel-gfx
  Cc: andi.shyti, chris.p.wilson, tomasz.mistat, jonathan.cavitt,
	rodrigo.vivi, gregory.f.germano, matthew.d.roper, nirmoy.das

Apply Wa_16018031267 / Wa_16018063123.  This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.

v2:
- Rename old platform check in second patch to match
  declaration in first patch.
- Refactor second patch name to match first patch.

v3:
- Move NEEDS_FASTCOLOR_BLT_WABB to intel_gt.h.
- Refactor NEEDS_FASTCOLOR_BLT_WABB to make it more
  streamlined to use.
- Stop dividing PAGE_SIZE by sizeof(u32) when computing
  ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.
- Reduce comment complexity.
- Fix several checkpatch warnings.

v4:
- Actually stop dividing PAGE_SIZE by sizeof(u32) when
  computing ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.

v5:
- Stop dividing PAGE_SIZE by sizeof(u32) in
  check_ring_start during lrc live selftest.

v6:
- Append MI_BATCH_BUFFER_END to end of all PER_CTX_BB
  command streams.
- No longer skip on empty, as command stream will never
  be empty (always contains at least MI_BATCH_BUFFER_END).
- No longer append MI_NOOP until cachline aligned (was a
  fragment from INDIRECT_CTX setup).

v7:
- Use 0x6b instead of 0 for color to maintain functionality.

v8:
- Revert v7.
- Add some reserved kernel space per vm to run the
  workaround on.

v9:
- Hide reserved kernel space per vm from userspace.

v10:
- Revert v7 properly.
- Test on updated IGT.

Test-with: 20230919170230.3307408-1-jonathan.cavitt@intel.com

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Tomasz Mistat <tomasz.mistat@intel.com>
CC: Gregory F Germano <gregory.f.germano@intel.com>
CC: Matt Roper <matthew.d.roper@intel.com>
CC: James Ausmus <james.ausmus@intel.com>
CC: Chris Wilson <chris.p.wilson@linux.intel.com>
CC: Andi Shyti <andi.shyti@intel.com>

Jonathan Cavitt (3):
  drm/i915: Reserve some kernel space per vm
  drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
  drm/i915: Set copy engine arbitration for Wa_16018031267 /
    Wa_16018063123

 drivers/gpu/drm/i915/gt/gen8_ppgtt.c        |   7 ++
 drivers/gpu/drm/i915/gt/intel_engine_regs.h |   6 ++
 drivers/gpu/drm/i915/gt/intel_gt.h          |   4 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h    |   2 +
 drivers/gpu/drm/i915/gt/intel_gtt.h         |   1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c         | 100 +++++++++++++++++++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c |   5 +
 drivers/gpu/drm/i915/gt/selftest_lrc.c      |  65 +++++++++----
 8 files changed, 169 insertions(+), 21 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v9 0/3] Apply Wa_16018031267 / Wa_16018063123
@ 2023-09-12 14:19 Jonathan Cavitt
  2023-09-13 21:37 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork
  0 siblings, 1 reply; 25+ messages in thread
From: Jonathan Cavitt @ 2023-09-12 14:19 UTC (permalink / raw)
  To: intel-gfx
  Cc: andi.shyti, chris.p.wilson, tomasz.mistat, jonathan.cavitt,
	rodrigo.vivi, gregory.f.germano, matthew.d.roper, nirmoy.das

Apply Wa_16018031267 / Wa_16018063123.  This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.

v2:
- Rename old platform check in second patch to match
  declaration in first patch.
- Refactor second patch name to match first patch.

v3:
- Move NEEDS_FASTCOLOR_BLT_WABB to intel_gt.h.
- Refactor NEEDS_FASTCOLOR_BLT_WABB to make it more
  streamlined to use.
- Stop dividing PAGE_SIZE by sizeof(u32) when computing
  ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.
- Reduce comment complexity.
- Fix several checkpatch warnings.

v4:
- Actually stop dividing PAGE_SIZE by sizeof(u32) when
  computing ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.

v5:
- Stop dividing PAGE_SIZE by sizeof(u32) in
  check_ring_start during lrc live selftest.

v6:
- Append MI_BATCH_BUFFER_END to end of all PER_CTX_BB
  command streams.
- No longer skip on empty, as command stream will never
  be empty (always contains at least MI_BATCH_BUFFER_END).
- No longer append MI_NOOP until cachline aligned (was a
  fragment from INDIRECT_CTX setup).

v7:
- Use 0x6b instead of 0 for color to maintain functionality.

v8:
- Revert v7.
- Add some reserved kernel space per vm to run the
  workaround on.

v9:
- Hide reserved kernel space per vm from userspace.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Tomasz Mistat <tomasz.mistat@intel.com>
CC: Gregory F Germano <gregory.f.germano@intel.com>
CC: Matt Roper <matthew.d.roper@intel.com>
CC: James Ausmus <james.ausmus@intel.com>
CC: Chris Wilson <chris.p.wilson@linux.intel.com>
CC: Andi Shyti <andi.shyti@intel.com>

Jonathan Cavitt (3):
  drm/i915: Reserve some kernel space per vm
  drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
  drm/i915: Set copy engine arbitration for Wa_16018031267 /
    Wa_16018063123

 drivers/gpu/drm/i915/gt/gen8_ppgtt.c        |   7 ++
 drivers/gpu/drm/i915/gt/intel_engine_regs.h |   6 ++
 drivers/gpu/drm/i915/gt/intel_gt.h          |   4 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h    |   2 +
 drivers/gpu/drm/i915/gt/intel_gtt.h         |   1 +
 drivers/gpu/drm/i915/gt/intel_lrc.c         | 101 +++++++++++++++++++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c |   5 +
 drivers/gpu/drm/i915/gt/selftest_lrc.c      |  65 +++++++++----
 8 files changed, 170 insertions(+), 21 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v6 0/2] Apply Wa_16018031267 / Wa_16018063123
@ 2023-09-05 20:19 Jonathan Cavitt
  2023-09-06 14:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork
  0 siblings, 1 reply; 25+ messages in thread
From: Jonathan Cavitt @ 2023-09-05 20:19 UTC (permalink / raw)
  To: intel-gfx
  Cc: tomasz.mistat, jonathan.cavitt, rodrigo.vivi, gregory.f.germano,
	matthew.d.roper, nirmoy.das

Apply Wa_16018031267 / Wa_16018063123.  This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.

v2:
- Rename old platform check in second patch to match
  declaration in first patch.
- Refactor second patch name to match first patch.

v3:
- Move NEEDS_FASTCOLOR_BLT_WABB to intel_gt.h.
- Refactor NEEDS_FASTCOLOR_BLT_WABB to make it more
  streamlined to use.
- Stop dividing PAGE_SIZE by sizeof(u32) when computing
  ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.
- Reduce comment complexity.
- Fix several checkpatch warnings.

v4:
- Actually stop dividing PAGE_SIZE by sizeof(u32) when
  computing ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.

v5:
- Stop dividing PAGE_SIZE by sizeof(u32) in
  check_ring_start during lrc live selftest.

v6:
- Append MI_BATCH_BUFFER_END to end of all PER_CTX_BB
  command streams.
- No longer skip on empty, as command stream will never
  be empty (always contains at least MI_BATCH_BUFFER_END).
- No longer append MI_NOOP until cachline aligned (was a
  fragment from INDIRECT_CTX setup).

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Tomasz Mistat <tomasz.mistat@intel.com>
CC: Gregory F Germano <gregory.f.germano@intel.com>
CC: Matt Roper <matthew.d.roper@intel.com>
CC: James Ausmus <james.ausmus@intel.com>

Jonathan Cavitt (2):
  drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
  drm/i915: Set copy engine arbitration for Wa_16018031267 /
    Wa_16018063123

 drivers/gpu/drm/i915/gt/intel_engine_regs.h |   6 ++
 drivers/gpu/drm/i915/gt/intel_gt.h          |   4 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h    |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc.c         | 101 +++++++++++++++++++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c |   5 +
 drivers/gpu/drm/i915/gt/selftest_lrc.c      |  65 +++++++++----
 6 files changed, 162 insertions(+), 21 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v5 0/2] Apply Wa_16018031267 / Wa_16018063123
@ 2023-09-01 15:00 Jonathan Cavitt
  2023-09-05 22:00 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork
  0 siblings, 1 reply; 25+ messages in thread
From: Jonathan Cavitt @ 2023-09-01 15:00 UTC (permalink / raw)
  To: intel-gfx
  Cc: tomasz.mistat, jonathan.cavitt, rodrigo.vivi, gregory.f.germano,
	matthew.d.roper, nirmoy.das

Apply Wa_16018031267 / Wa_16018063123.  This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.

v2:
- Rename old platform check in second patch to match
  declaration in first patch.
- Refactor second patch name to match first patch.

v3:
- Move NEEDS_FASTCOLOR_BLT_WABB to intel_gt.h.
- Refactor NEEDS_FASTCOLOR_BLT_WABB to make it more
  streamlined to use.
- Stop dividing PAGE_SIZE by sizeof(u32) when computing
  ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.
- Reduce comment complexity.
- Fix several checkpatch warnings.

v4:
- Actually stop dividing PAGE_SIZE by sizeof(u32) when
  computing ctx_bb_ggtt_addr for lrc_setup_bb_per_ctx.

v5:
- Stop dividing PAGE_SIZE by sizeof(u32) in
  check_ring_start during lrc live selftest.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Tomasz Mistat <tomasz.mistat@intel.com>
CC: Gregory F Germano <gregory.f.germano@intel.com>
CC: Matt Roper <matthew.d.roper@intel.com>
CC: James Ausmus <james.ausmus@intel.com>

Jonathan Cavitt (2):
  drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
  drm/i915: Set copy engine arbitration for Wa_16018031267 /
    Wa_16018063123

 drivers/gpu/drm/i915/gt/intel_engine_regs.h |   6 ++
 drivers/gpu/drm/i915/gt/intel_gt.h          |   4 +
 drivers/gpu/drm/i915/gt/intel_gt_types.h    |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc.c         | 107 +++++++++++++++++++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c |   5 +
 drivers/gpu/drm/i915/gt/selftest_lrc.c      |  65 ++++++++----
 6 files changed, 168 insertions(+), 21 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [Intel-gfx] [PATCH v2 0/2] Apply Wa_16018031267 / Wa_16018063123
@ 2023-08-23 18:51 Jonathan Cavitt
  2023-08-23 21:30 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork
  0 siblings, 1 reply; 25+ messages in thread
From: Jonathan Cavitt @ 2023-08-23 18:51 UTC (permalink / raw)
  To: intel-gfx
  Cc: tomasz.mistat, jonathan.cavitt, rodrigo.vivi, gregory.f.germano,
	matthew.d.roper, nirmoy.das

Apply Wa_16018031267 / Wa_16018063123.  This necessitates submitting a
fastcolor blit as WABB and setting the copy engine arbitration to
round-robin mode.

v2:
- Rename old platform check in second patch to match
  declaration in first patch.
- Refactor second patch name to match first patch.

Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
CC: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
CC: Rodrigo Vivi <rodrigo.vivi@intel.com>
CC: Tomasz Mistat <tomasz.mistat@intel.com>
CC: Gregory F Germano <gregory.f.germano@intel.com>
CC: Matt Roper <matthew.d.roper@intel.com>
CC: James Ausmus <james.ausmus@intel.com>

Nirmoy Das (2):
  drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123
  drm/i915: Set copy engine arbitration for Wa_16018031267 /
    Wa_16018063123

 drivers/gpu/drm/i915/gt/intel_engine_regs.h |   6 ++
 drivers/gpu/drm/i915/gt/intel_gt_types.h    |   3 +
 drivers/gpu/drm/i915/gt/intel_lrc.c         | 114 +++++++++++++++++++-
 drivers/gpu/drm/i915/gt/intel_workarounds.c |   6 ++
 drivers/gpu/drm/i915/gt/selftest_lrc.c      |  65 +++++++----
 drivers/gpu/drm/i915/i915_drv.h             |   5 +
 6 files changed, 178 insertions(+), 21 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 25+ messages in thread

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2023-10-26 18:36 [Intel-gfx] [PATCH v6 0/4] Apply Wa_16018031267 / Wa_16018063123 Andrzej Hajda
2023-10-26 18:36 ` [Intel-gfx] [PATCH v6 1/4] drm/i915: Reserve some kernel space per vm Andrzej Hajda
2023-10-26 18:36 ` [Intel-gfx] [PATCH v6 2/4] drm/i915: Add WABB blit for Wa_16018031267 / Wa_16018063123 Andrzej Hajda
2023-10-26 18:36 ` [Intel-gfx] [PATCH v6 3/4] drm/i915/gt: add selftest to exercise WABB Andrzej Hajda
2023-10-26 18:36 ` [Intel-gfx] [PATCH v6 4/4] drm/i915: Set copy engine arbitration for Wa_16018031267 / Wa_16018063123 Andrzej Hajda
2023-10-27  5:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply " Patchwork
2023-10-27  5:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-27  5:34 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-27  6:06   ` Andrzej Hajda
2023-10-27  8:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork
2023-10-27  8:13 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-27  8:32 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-27 10:11   ` Andrzej Hajda
2023-10-28  0:34 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Apply Wa_16018031267 / Wa_16018063123 (rev3) Patchwork
2023-10-28  0:34 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-28  0:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-30 22:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-31  7:42   ` Andrzej Hajda
2023-10-31 12:19 ` [Intel-gfx] [PATCH v6 0/4] Apply Wa_16018031267 / Wa_16018063123 Andrzej Hajda
  -- strict thread matches above, loose matches on Subject: below --
2023-09-20 21:07 [Intel-gfx] [PATCH v12 " Jonathan Cavitt
2023-09-22  3:12 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork
2023-09-19 17:16 [Intel-gfx] [PATCH v10 0/3] Apply Wa_16018031267 / Wa_16018063123 Jonathan Cavitt
2023-09-19 22:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork
2023-09-12 14:19 [Intel-gfx] [PATCH v9 0/3] Apply Wa_16018031267 / Wa_16018063123 Jonathan Cavitt
2023-09-13 21:37 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork
2023-09-05 20:19 [Intel-gfx] [PATCH v6 0/2] Apply Wa_16018031267 / Wa_16018063123 Jonathan Cavitt
2023-09-06 14:59 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork
2023-09-01 15:00 [Intel-gfx] [PATCH v5 0/2] Apply Wa_16018031267 / Wa_16018063123 Jonathan Cavitt
2023-09-05 22:00 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork
2023-08-23 18:51 [Intel-gfx] [PATCH v2 0/2] Apply Wa_16018031267 / Wa_16018063123 Jonathan Cavitt
2023-08-23 21:30 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for Apply Wa_16018031267 / Wa_16018063123 (rev2) Patchwork

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