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From: mdalam@codeaurora.org
To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
	boris.brezillon@collabora.com, manivannan.sadhasivam@linaro.org,
	linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: sricharan@codeaurora.org
Subject: Re: [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset
Date: Fri, 05 Feb 2021 23:26:33 +0530	[thread overview]
Message-ID: <7ca35f62c4d3ba7833e192cab3a2701d@codeaurora.org> (raw)
In-Reply-To: <1612037236-7954-1-git-send-email-mdalam@codeaurora.org>

On 2021-01-31 01:37, Md Sadre Alam wrote:
> This change will remove unused register name macro NAND_DEV1_ECC_CFG.
> Since this register was only available in QPIC version 1.4.20 ipq40xx
> and it was not used. In QPIC version 1.5 on wards this register got
> removed.In QPIC version 2.0 0x2c offset is updated with register
> NAND_AUTO_STATUS_EN So adding this register macro NAND_AUTO_STATUS_EN
> with offset 0x2c.
> 
> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>

   Ping! Is any additional info needed for this patch ?

> ---
>  drivers/mtd/nand/raw/qcom_nandc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
> b/drivers/mtd/nand/raw/qcom_nandc.c
> index 9484be8..c238a35 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -27,7 +27,7 @@
>  #define	NAND_DEV0_CFG0			0x20
>  #define	NAND_DEV0_CFG1			0x24
>  #define	NAND_DEV0_ECC_CFG		0x28
> -#define	NAND_DEV1_ECC_CFG		0x2c
> +#define	NAND_AUTO_STATUS_EN		0x2c
>  #define	NAND_DEV1_CFG0			0x30
>  #define	NAND_DEV1_CFG1			0x34
>  #define	NAND_READ_ID			0x40

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WARNING: multiple messages have this Message-ID (diff)
From: mdalam@codeaurora.org
To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
	boris.brezillon@collabora.com, manivannan.sadhasivam@linaro.org,
	linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Cc: sricharan@codeaurora.org
Subject: Re: [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset
Date: Fri, 05 Feb 2021 23:26:33 +0530	[thread overview]
Message-ID: <7ca35f62c4d3ba7833e192cab3a2701d@codeaurora.org> (raw)
In-Reply-To: <1612037236-7954-1-git-send-email-mdalam@codeaurora.org>

On 2021-01-31 01:37, Md Sadre Alam wrote:
> This change will remove unused register name macro NAND_DEV1_ECC_CFG.
> Since this register was only available in QPIC version 1.4.20 ipq40xx
> and it was not used. In QPIC version 1.5 on wards this register got
> removed.In QPIC version 2.0 0x2c offset is updated with register
> NAND_AUTO_STATUS_EN So adding this register macro NAND_AUTO_STATUS_EN
> with offset 0x2c.
> 
> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>

   Ping! Is any additional info needed for this patch ?

> ---
>  drivers/mtd/nand/raw/qcom_nandc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
> b/drivers/mtd/nand/raw/qcom_nandc.c
> index 9484be8..c238a35 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -27,7 +27,7 @@
>  #define	NAND_DEV0_CFG0			0x20
>  #define	NAND_DEV0_CFG1			0x24
>  #define	NAND_DEV0_ECC_CFG		0x28
> -#define	NAND_DEV1_ECC_CFG		0x2c
> +#define	NAND_AUTO_STATUS_EN		0x2c
>  #define	NAND_DEV1_CFG0			0x30
>  #define	NAND_DEV1_CFG1			0x34
>  #define	NAND_READ_ID			0x40

  reply	other threads:[~2021-02-05 17:57 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-30 20:07 [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset Md Sadre Alam
2021-01-30 20:07 ` Md Sadre Alam
2021-02-05 17:56 ` mdalam [this message]
2021-02-05 17:56   ` mdalam
2021-02-05 18:01   ` Miquel Raynal
2021-02-05 18:01     ` Miquel Raynal
2021-02-10  8:58 ` Manivannan Sadhasivam
2021-02-10  8:58   ` Manivannan Sadhasivam
2021-03-02 16:33 ` Miquel Raynal
2021-03-02 16:33   ` Miquel Raynal

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