[PATCH v2 00/19] hw/mips: Remove all uses of &first_cpu

[PATCH v2 00/19] hw/mips: Remove all uses of &first_cpu

[Philippe Mathieu-Daudé]

v2:
- Add documentation
- Reorder propagation to reduce code churn around &first_cpu

v1:
- Keep references to vCPUs in CPS and MaltaState,
- Refactor the MIPS Bootloader API to take CPU argument
- Access first CPU propagate from machine_init()

Based-on: <20250112215835.29320-1-philmd@linaro.org>
"hw/mips/loongson3: Remove uses of &first_cpu global"

Philippe Mathieu-Daudé (19):
  hw/mips/cps: Keep reference of vCPUs in MIPSCPSState
  hw/mips/malta: Check CPU index instead of using &first_cpu
  hw/mips/malta: Keep reference of vCPUs in MaltaState
  hw/mips/malta: Propagate MaltaState to write_bootloader()
  hw/mips/malta: Propagate MaltaState to bl_setup_gt64120_jump_kernel()
  hw/mips/boston: Replace bl_gen_write_ulong() -> bl_gen_write_u64()
  hw/mips/boston: Propagate CPU to gen_firmware()
  hw/mips/fuloong: Propagate CPU to write_bootloader()
  hw/mips/bootloader: Document public API
  hw/mips/bootloader: Propagate CPU to bl_gen_write_u[32,64,long]()
  hw/mips/bootloader: Propagate CPU to bl_gen_jump_[to,kernel]()
  hw/mips/bootloader: Propagate CPU env to bl_gen_load_ulong()
  hw/mips/bootloader: Propagate CPU env to bl_gen_[d]li()
  hw/mips/bootloader: Propagate CPU env to bl_gen_s[w,d]()
  hw/mips/bootloader: Propagate CPU env to bl_gen_jalr()
  hw/mips/bootloader: Propagate CPU env to bl_gen_dsll()
  hw/mips/bootloader: Propagate CPU env to bl_gen_nop()
  hw/mips/bootloader: Propagate CPU env to bootcpu_supports_isa()
  hw/mips/bootloader: Remove use of &first_cpu in bootcpu_supports_isa()

 include/hw/mips/bootloader.h |  69 +++++++++++++++++++--
 include/hw/mips/cps.h        |   1 +
 hw/mips/bootloader.c         | 113 ++++++++++++++++++++---------------
 hw/mips/boston.c             |  21 ++++---
 hw/mips/cps.c                |   4 +-
 hw/mips/fuloong2e.c          |   6 +-
 hw/mips/malta.c              |  60 +++++++++++--------
 7 files changed, 184 insertions(+), 90 deletions(-)

-- 
2.47.1

[PATCH v2 01/19] hw/mips/cps: Keep reference of vCPUs in MIPSCPSState

[Philippe Mathieu-Daudé]

When a QOM object create children with object_new(),
it is better to keep reference to them for further
use. In particular, this allow to remove one global
&first_cpu use.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/mips/cps.h | 1 +
 hw/mips/cps.c         | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/hw/mips/cps.h b/include/hw/mips/cps.h
index 05ef9f76b74..0968b57c5a0 100644
--- a/include/hw/mips/cps.h
+++ b/include/hw/mips/cps.h
@@ -40,6 +40,7 @@ struct MIPSCPSState {
     char *cpu_type;
     bool cpu_is_bigendian;
 
+    MIPSCPU **cpus;
     MemoryRegion container;
     MIPSGCRState gcr;
     MIPSGICState gic;
diff --git a/hw/mips/cps.c b/hw/mips/cps.c
index 293b405b965..494213b2ab6 100644
--- a/hw/mips/cps.c
+++ b/hw/mips/cps.c
@@ -73,6 +73,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
         return;
     }
 
+    s->cpus = g_new(MIPSCPU *, s->num_vp);
     for (int i = 0; i < s->num_vp; i++) {
         MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type));
         CPUMIPSState *env = &cpu->env;
@@ -91,6 +92,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
         if (!qdev_realize_and_unref(DEVICE(cpu), NULL, errp)) {
             return;
         }
+        s->cpus[i] = cpu;
 
         /* Init internal devices */
         cpu_mips_irq_init_cpu(cpu);
@@ -146,7 +148,7 @@ static void mips_cps_realize(DeviceState *dev, Error **errp)
                             sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
 
     /* Global Configuration Registers */
-    gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4;
+    gcr_base = s->cpus[0]->env.CP0_CMGCRBase << 4;
 
     object_initialize_child(OBJECT(dev), "gcr", &s->gcr, TYPE_MIPS_GCR);
     object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp,
-- 
2.47.1

[PATCH v2 02/19] hw/mips/malta: Check CPU index instead of using &first_cpu

[Philippe Mathieu-Daudé]

Since create_cpu_without_cps() creates the vCPUs iterating
up to the machine SMP count, it knows the first CPU is
created upon the first iteration, at index #0 :)

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/malta.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 4e9cccaa347..37be2330eda 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1042,12 +1042,13 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
         cpu_mips_irq_init_cpu(cpu);
         cpu_mips_clock_init(cpu);
         qemu_register_reset(main_cpu_reset, cpu);
-    }
 
-    cpu = MIPS_CPU(first_cpu);
-    env = &cpu->env;
-    *i8259_irq = env->irq[2];
-    *cbus_irq = env->irq[4];
+        if (i == 0) {
+            env = &cpu->env;
+            *i8259_irq = env->irq[2];
+            *cbus_irq = env->irq[4];
+        }
+    }
 }
 
 static void create_cps(MachineState *ms, MaltaState *s,
-- 
2.47.1

[PATCH v2 03/19] hw/mips/malta: Keep reference of vCPUs in MaltaState

[Philippe Mathieu-Daudé]

When a QOM object create children with object_new(),
it is better to keep reference to them for further
use. This will be helpful to remove &first_cpu uses
in few commits.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/malta.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 37be2330eda..090c2514354 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -107,6 +107,7 @@ struct MaltaState {
     SysBusDevice parent_obj;
 
     Clock *cpuclk;
+    MIPSCPU **cpus;
     MIPSCPSState cps;
 };
 
@@ -1037,6 +1038,7 @@ static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
     for (i = 0; i < ms->smp.cpus; i++) {
         cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk,
                                          TARGET_BIG_ENDIAN);
+        s->cpus[i] = cpu;
 
         /* Init internal devices */
         cpu_mips_irq_init_cpu(cpu);
@@ -1063,6 +1065,7 @@ static void create_cps(MachineState *ms, MaltaState *s,
                             &error_fatal);
     qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk);
     sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
+    memcpy(s->cpus, s->cps.cpus, ms->smp.cpus * sizeof(MIPSCPU *));
 
     sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
 
@@ -1070,9 +1073,11 @@ static void create_cps(MachineState *ms, MaltaState *s,
     *cbus_irq = NULL;
 }
 
-static void mips_create_cpu(MachineState *ms, MaltaState *s,
-                            qemu_irq *cbus_irq, qemu_irq *i8259_irq)
+/* Initialize MaltaState::cpus[] */
+static void mips_create_cpus(MachineState *ms, MaltaState *s,
+                             qemu_irq *cbus_irq, qemu_irq *i8259_irq)
 {
+    s->cpus = g_new(MIPSCPU *, ms->smp.cpus);
     if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) {
         create_cps(ms, s, cbus_irq, i8259_irq);
     } else {
@@ -1111,7 +1116,7 @@ void mips_malta_init(MachineState *machine)
     sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);
 
     /* create CPU */
-    mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
+    mips_create_cpus(machine, s, &cbus_irq, &i8259_irq);
 
     /* allocate RAM */
     if (ram_size > 2 * GiB) {
-- 
2.47.1

[PATCH v2 04/19] hw/mips/malta: Propagate MaltaState to write_bootloader()

[Philippe Mathieu-Daudé]

Pass MaltaState as argument to write_bootloader() so next
commit can propagate it to bl_setup_gt64120_jump_kernel().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/malta.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 090c2514354..ec8fd954b4b 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -692,7 +692,8 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr,
                        kernel_entry);
 }
 
-static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
+static void write_bootloader_nanomips(MaltaState *s,
+                                      uint8_t *base, uint64_t run_addr,
                                       uint64_t kernel_entry)
 {
     uint16_t *p;
@@ -744,7 +745,8 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
  *   a2 - 32-bit address of the environment variables table
  *   a3 - RAM size in bytes
  */
-static void write_bootloader(uint8_t *base, uint64_t run_addr,
+static void write_bootloader(MaltaState *s,
+                             uint8_t *base, uint64_t run_addr,
                              uint64_t kernel_entry)
 {
     uint32_t *p;
@@ -1172,10 +1174,10 @@ void mips_malta_init(MachineState *machine)
         kernel_entry = load_kernel();
 
         if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
-            write_bootloader(memory_region_get_ram_ptr(bios),
+            write_bootloader(s, memory_region_get_ram_ptr(bios),
                              bootloader_run_addr, kernel_entry);
         } else {
-            write_bootloader_nanomips(memory_region_get_ram_ptr(bios),
+            write_bootloader_nanomips(s, memory_region_get_ram_ptr(bios),
                                       bootloader_run_addr, kernel_entry);
         }
     } else {
-- 
2.47.1

[PATCH v2 05/19] hw/mips/malta: Propagate MaltaState to bl_setup_gt64120_jump_kernel()

[Philippe Mathieu-Daudé]

Propagate MaltaState to bl_setup_gt64120_jump_kernel() so
it can access the MaltaState::cpus[] array.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/malta.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index ec8fd954b4b..f7eb990c629 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -620,7 +620,8 @@ static void network_init(PCIBus *pci_bus)
     pci_init_nic_devices(pci_bus, "pcnet");
 }
 
-static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr,
+static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p,
+                                         uint64_t run_addr,
                                          uint64_t kernel_entry)
 {
     static const char pci_pins_cfg[PCI_NUM_PINS] = {
@@ -720,7 +721,7 @@ static void write_bootloader_nanomips(MaltaState *s,
 
     /* to_here: */
 
-    bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
+    bl_setup_gt64120_jump_kernel(s, (void **)&p, run_addr, kernel_entry);
 }
 
 /*
@@ -786,7 +787,7 @@ static void write_bootloader(MaltaState *s,
      *
      */
 
-    bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
+    bl_setup_gt64120_jump_kernel(s, (void **)&p, run_addr, kernel_entry);
 
     /* YAMON subroutines */
     p = (uint32_t *) (base + 0x800);
-- 
2.47.1

[PATCH v2 06/19] hw/mips/boston: Replace bl_gen_write_ulong() -> bl_gen_write_u64()

[Philippe Mathieu-Daudé]

"exec/hwaddr.h" defines:

  typedef uint64_t hwaddr;

  typedef struct MemMapEntry {
      hwaddr base;
      hwaddr size;
  } MemMapEntry;

Since MemMapEntry::base is always of type uint64_t,
we can directly use bl_gen_write_u64().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/boston.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 67044af962a..63dc654192a 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -329,20 +329,20 @@ static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr)
 
     /* Move CM GCRs */
     regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS),
-    bl_gen_write_ulong(&p, regaddr,
-                       boston_memmap[BOSTON_CM].base);
+    bl_gen_write_u64(&p, regaddr,
+                     boston_memmap[BOSTON_CM].base);
 
     /* Move & enable GIC GCRs */
     regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
                                            + GCR_GIC_BASE_OFS),
-    bl_gen_write_ulong(&p, regaddr,
-                       boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK);
+    bl_gen_write_u64(&p, regaddr,
+                     boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK);
 
     /* Move & enable CPC GCRs */
     regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
                                            + GCR_CPC_BASE_OFS),
-    bl_gen_write_ulong(&p, regaddr,
-                       boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK);
+    bl_gen_write_u64(&p, regaddr,
+                     boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK);
 
     /*
      * Setup argument registers to follow the UHI boot protocol:
-- 
2.47.1

[PATCH v2 07/19] hw/mips/boston: Propagate CPU to gen_firmware()

[Philippe Mathieu-Daudé]

Propagate a CPU to gen_firmware(). Since we expect the first CPU
to run the firmware, get it from the CPS in boston_mach_init(),
resolving it using its QOM path.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/boston.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 63dc654192a..491e1c4f7ea 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -323,7 +323,8 @@ static void boston_register_types(void)
 }
 type_init(boston_register_types)
 
-static void gen_firmware(void *p, hwaddr kernel_entry, hwaddr fdt_addr)
+static void gen_firmware(const MIPSCPU *cpu, void *p,
+                         hwaddr kernel_entry, hwaddr fdt_addr)
 {
     uint64_t regaddr;
 
@@ -825,7 +826,9 @@ static void boston_mach_init(MachineState *machine)
             }
         }
 
-        gen_firmware(memory_region_get_ram_ptr(flash) + 0x7c00000,
+        gen_firmware(MIPS_CPU(object_resolve_path_component(OBJECT(&s->cps),
+                                                            "cpu[0]")),
+                     memory_region_get_ram_ptr(flash) + 0x7c00000,
                      s->kernel_entry, s->fdt_base);
     } else if (!qtest_enabled()) {
         error_report("Please provide either a -kernel or -bios argument");
-- 
2.47.1

[PATCH v2 08/19] hw/mips/fuloong: Propagate CPU to write_bootloader()

[Philippe Mathieu-Daudé]

mips_fuloong2e_init() created the vCPU so has its reference,
propagate it to write_bootloader(), removing the &first_cpu use.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/fuloong2e.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 16b6a5129e7..c4080a8a6e3 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -163,7 +163,7 @@ static uint64_t load_kernel(MIPSCPU *cpu)
     return kernel_entry;
 }
 
-static void write_bootloader(CPUMIPSState *env, uint8_t *base,
+static void write_bootloader(const MIPSCPU *cpu, uint8_t *base,
                              uint64_t kernel_addr)
 {
     uint32_t *p;
@@ -258,7 +258,7 @@ static void mips_fuloong2e_init(MachineState *machine)
         loaderparams.kernel_cmdline = kernel_cmdline;
         loaderparams.initrd_filename = initrd_filename;
         kernel_entry = load_kernel(cpu);
-        write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
+        write_bootloader(cpu, memory_region_get_ram_ptr(bios), kernel_entry);
     } else {
         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
                                   machine->firmware ?: FULOONG_BIOSNAME);
-- 
2.47.1

[PATCH v2 09/19] hw/mips/bootloader: Document public API

[Philippe Mathieu-Daudé]

Document bl_gen_write_u[32,64,long]() and bl_gen_jump_[to,kernel]()
prototypes.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/mips/bootloader.h | 50 ++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
index c32f6c28356..8533a16ca62 100644
--- a/include/hw/mips/bootloader.h
+++ b/include/hw/mips/bootloader.h
@@ -11,7 +11,30 @@
 
 #include "exec/cpu-defs.h"
 
+/**
+ * bl_gen_jump_to: Generate bootloader code to jump to an address
+ *
+ * @ptr: Pointer to buffer where to write the bootloader code
+ * @jump_addr: Address to jump to
+ */
 void bl_gen_jump_to(void **ptr, target_ulong jump_addr);
+
+/**
+ * bl_gen_jump_kernel: Generate bootloader code to jump to a Linux kernel
+ *
+ * @ptr: Pointer to buffer where to write the bootloader code
+ * @set_sp: Whether to set $sp register
+ * @set_a0: Whether to set $a0 register
+ * @set_a1: Whether to set $a1 register
+ * @set_a2: Whether to set $a2 register
+ * @set_a3: Whether to set $a3 register
+ * @sp: Value to set $sp to if @set_sp is set
+ * @a0: Value to set $a0 to if @set_a0 is set
+ * @a1: Value to set $a0 to if @set_a1 is set
+ * @a2: Value to set $a0 to if @set_a2 is set
+ * @a3: Value to set $a0 to if @set_a3 is set
+ * @kernel_addr: Start address of the kernel to jump to
+ */
 void bl_gen_jump_kernel(void **ptr,
                         bool set_sp, target_ulong sp,
                         bool set_a0, target_ulong a0,
@@ -19,8 +42,35 @@ void bl_gen_jump_kernel(void **ptr,
                         bool set_a2, target_ulong a2,
                         bool set_a3, target_ulong a3,
                         target_ulong kernel_addr);
+
+/**
+ * bl_gen_write_ulong: Generate bootloader code to write an unsigned long
+ *                     value at an address
+ *
+ * @ptr: Pointer to buffer where to write the bootloader code
+ * @addr: Address to write to
+ * @val: Value to write at @addr
+ */
 void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val);
+
+/**
+ * bl_gen_write_u32: Generate bootloader code to write a 32-bit unsigned
+ *                   value at an address
+ *
+ * @ptr: Pointer to buffer where to write the bootloader code
+ * @addr: Address to write to
+ * @val: Value to write at @addr
+ */
 void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val);
+
+/**
+ * bl_gen_write_u64: Generate bootloader code to write a 64-bit unsigned
+ *                   value at an address
+ *
+ * @ptr: Pointer to buffer where to write the bootloader code
+ * @addr: Address to write to
+ * @val: Value to write at @addr
+ */
 void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val);
 
 #endif
-- 
2.47.1

[PATCH v2 10/19] hw/mips/bootloader: Propagate CPU to bl_gen_write_u[32, 64, long]()

[Philippe Mathieu-Daudé]

Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_write_u32(), bl_gen_write_u64() and
bl_gen_write_ulong() functions.

For the Malta machine in bl_setup_gt64120_jump_kernel(),
pass its first CPU (the one we want to start running the
bootloader).

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/mips/bootloader.h | 13 ++++++++++---
 hw/mips/bootloader.c         |  9 ++++++---
 hw/mips/boston.c             |  6 +++---
 hw/mips/malta.c              | 19 ++++++++++---------
 4 files changed, 29 insertions(+), 18 deletions(-)

diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
index 8533a16ca62..bc54ea8c7fb 100644
--- a/include/hw/mips/bootloader.h
+++ b/include/hw/mips/bootloader.h
@@ -10,6 +10,7 @@
 #define HW_MIPS_BOOTLOADER_H
 
 #include "exec/cpu-defs.h"
+#include "target/mips/cpu-qom.h"
 
 /**
  * bl_gen_jump_to: Generate bootloader code to jump to an address
@@ -47,30 +48,36 @@ void bl_gen_jump_kernel(void **ptr,
  * bl_gen_write_ulong: Generate bootloader code to write an unsigned long
  *                     value at an address
  *
+ * @cpu: The MIPS CPU which will run the bootloader code
  * @ptr: Pointer to buffer where to write the bootloader code
  * @addr: Address to write to
  * @val: Value to write at @addr
  */
-void bl_gen_write_ulong(void **ptr, target_ulong addr, target_ulong val);
+void bl_gen_write_ulong(const MIPSCPU *cpu, void **ptr,
+                        target_ulong addr, target_ulong val);
 
 /**
  * bl_gen_write_u32: Generate bootloader code to write a 32-bit unsigned
  *                   value at an address
  *
+ * @cpu: The MIPS CPU which will run the bootloader code
  * @ptr: Pointer to buffer where to write the bootloader code
  * @addr: Address to write to
  * @val: Value to write at @addr
  */
-void bl_gen_write_u32(void **ptr, target_ulong addr, uint32_t val);
+void bl_gen_write_u32(const MIPSCPU *cpu, void **ptr,
+                      target_ulong addr, uint32_t val);
 
 /**
  * bl_gen_write_u64: Generate bootloader code to write a 64-bit unsigned
  *                   value at an address
  *
+ * @cpu: The MIPS CPU which will run the bootloader code
  * @ptr: Pointer to buffer where to write the bootloader code
  * @addr: Address to write to
  * @val: Value to write at @addr
  */
-void bl_gen_write_u64(void **ptr, target_ulong addr, uint64_t val);
+void bl_gen_write_u64(const MIPSCPU *cpu, void **ptr,
+                      target_ulong addr, uint64_t val);
 
 #endif
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 1dd6ef20968..7db3bf7511f 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -277,7 +277,8 @@ void bl_gen_jump_kernel(void **p,
     bl_gen_jump_to(p, kernel_addr);
 }
 
-void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val)
+void bl_gen_write_ulong(const MIPSCPU *cpu, void **p,
+                        target_ulong addr, target_ulong val)
 {
     bl_gen_load_ulong(p, BL_REG_K0, val);
     bl_gen_load_ulong(p, BL_REG_K1, addr);
@@ -288,14 +289,16 @@ void bl_gen_write_ulong(void **p, target_ulong addr, target_ulong val)
     }
 }
 
-void bl_gen_write_u32(void **p, target_ulong addr, uint32_t val)
+void bl_gen_write_u32(const MIPSCPU *cpu, void **p,
+                      target_ulong addr, uint32_t val)
 {
     bl_gen_li(p, BL_REG_K0, val);
     bl_gen_load_ulong(p, BL_REG_K1, addr);
     bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
 }
 
-void bl_gen_write_u64(void **p, target_ulong addr, uint64_t val)
+void bl_gen_write_u64(const MIPSCPU *cpu, void **p,
+                      target_ulong addr, uint64_t val)
 {
     bl_gen_dli(p, BL_REG_K0, val);
     bl_gen_load_ulong(p, BL_REG_K1, addr);
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index 491e1c4f7ea..b646c104df7 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -330,19 +330,19 @@ static void gen_firmware(const MIPSCPU *cpu, void *p,
 
     /* Move CM GCRs */
     regaddr = cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS),
-    bl_gen_write_u64(&p, regaddr,
+    bl_gen_write_u64(cpu, &p, regaddr,
                      boston_memmap[BOSTON_CM].base);
 
     /* Move & enable GIC GCRs */
     regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
                                            + GCR_GIC_BASE_OFS),
-    bl_gen_write_u64(&p, regaddr,
+    bl_gen_write_u64(cpu, &p, regaddr,
                      boston_memmap[BOSTON_GIC].base | GCR_GIC_BASE_GICEN_MSK);
 
     /* Move & enable CPC GCRs */
     regaddr = cpu_mips_phys_to_kseg1(NULL, boston_memmap[BOSTON_CM].base
                                            + GCR_CPC_BASE_OFS),
-    bl_gen_write_u64(&p, regaddr,
+    bl_gen_write_u64(cpu, &p, regaddr,
                      boston_memmap[BOSTON_CPC].base | GCR_CPC_BASE_CPCEN_MSK);
 
     /*
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index f7eb990c629..9bc3fc9da3e 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -627,6 +627,7 @@ static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p,
     static const char pci_pins_cfg[PCI_NUM_PINS] = {
         10, 10, 11, 11 /* PIIX IRQRC[A:D] */
     };
+    const MIPSCPU *cpu = s->cpus[0];
 
     /* Bus endianness is always reversed */
 #if TARGET_BIG_ENDIAN
@@ -638,29 +639,29 @@ static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p,
     /* setup MEM-to-PCI0 mapping as done by YAMON */
 
     /* move GT64120 registers from 0x14000000 to 0x1be00000 */
-    bl_gen_write_u32(p, /* GT_ISD */
+    bl_gen_write_u32(cpu, p, /* GT_ISD */
                      cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
                      cpu_to_gt32(0x1be00000 << 3));
 
     /* setup PCI0 io window to 0x18000000-0x181fffff */
-    bl_gen_write_u32(p, /* GT_PCI0IOLD */
+    bl_gen_write_u32(cpu, p, /* GT_PCI0IOLD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
                      cpu_to_gt32(0x18000000 << 3));
-    bl_gen_write_u32(p, /* GT_PCI0IOHD */
+    bl_gen_write_u32(cpu, p, /* GT_PCI0IOHD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
                      cpu_to_gt32(0x08000000 << 3));
 
     /* setup PCI0 mem windows */
-    bl_gen_write_u32(p, /* GT_PCI0M0LD */
+    bl_gen_write_u32(cpu, p, /* GT_PCI0M0LD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
                      cpu_to_gt32(0x10000000 << 3));
-    bl_gen_write_u32(p, /* GT_PCI0M0HD */
+    bl_gen_write_u32(cpu, p, /* GT_PCI0M0HD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
                      cpu_to_gt32(0x07e00000 << 3));
-    bl_gen_write_u32(p, /* GT_PCI0M1LD */
+    bl_gen_write_u32(cpu, p, /* GT_PCI0M1LD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
                      cpu_to_gt32(0x18200000 << 3));
-    bl_gen_write_u32(p, /* GT_PCI0M1HD */
+    bl_gen_write_u32(cpu, p, /* GT_PCI0M1HD */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
                      cpu_to_gt32(0x0bc00000 << 3));
 
@@ -671,12 +672,12 @@ static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p,
      * Load the PIIX IRQC[A:D] routing config address, then
      * write routing configuration to the config data register.
      */
-    bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */
+    bl_gen_write_u32(cpu, p, /* GT_PCI0_CFGADDR */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8),
                      tswap32((1 << 31) /* ConfigEn */
                              | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8
                              | PIIX_PIRQCA));
-    bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */
+    bl_gen_write_u32(cpu, p, /* GT_PCI0_CFGDATA */
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc),
                      tswap32(ldl_be_p(pci_pins_cfg)));
 
-- 
2.47.1

[PATCH v2 11/19] hw/mips/bootloader: Propagate CPU to bl_gen_jump_[to, kernel]()

[Philippe Mathieu-Daudé]

Propagate the target agnostic CPU pointer to the publicly
declared bl_gen_jump_to() and bl_gen_jump_kernel() functions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/mips/bootloader.h | 6 ++++--
 hw/mips/bootloader.c         | 6 +++---
 hw/mips/boston.c             | 2 +-
 hw/mips/fuloong2e.c          | 2 +-
 hw/mips/malta.c              | 2 +-
 5 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h
index bc54ea8c7fb..173410f54ea 100644
--- a/include/hw/mips/bootloader.h
+++ b/include/hw/mips/bootloader.h
@@ -15,14 +15,16 @@
 /**
  * bl_gen_jump_to: Generate bootloader code to jump to an address
  *
+ * @cpu: The MIPS CPU which will run the bootloader code
  * @ptr: Pointer to buffer where to write the bootloader code
  * @jump_addr: Address to jump to
  */
-void bl_gen_jump_to(void **ptr, target_ulong jump_addr);
+void bl_gen_jump_to(const MIPSCPU *cpu, void **ptr, target_ulong jump_addr);
 
 /**
  * bl_gen_jump_kernel: Generate bootloader code to jump to a Linux kernel
  *
+ * @cpu: The MIPS CPU which will run the bootloader code
  * @ptr: Pointer to buffer where to write the bootloader code
  * @set_sp: Whether to set $sp register
  * @set_a0: Whether to set $a0 register
@@ -36,7 +38,7 @@ void bl_gen_jump_to(void **ptr, target_ulong jump_addr);
  * @a3: Value to set $a0 to if @set_a3 is set
  * @kernel_addr: Start address of the kernel to jump to
  */
-void bl_gen_jump_kernel(void **ptr,
+void bl_gen_jump_kernel(const MIPSCPU *cpu, void **ptr,
                         bool set_sp, target_ulong sp,
                         bool set_a0, target_ulong a0,
                         bool set_a1, target_ulong a1,
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 7db3bf7511f..9b074d9903b 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -243,14 +243,14 @@ static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm)
 }
 
 /* Helpers */
-void bl_gen_jump_to(void **p, target_ulong jump_addr)
+void bl_gen_jump_to(const MIPSCPU *cpu, void **p, target_ulong jump_addr)
 {
     bl_gen_load_ulong(p, BL_REG_T9, jump_addr);
     bl_gen_jalr(p, BL_REG_T9);
     bl_gen_nop(p); /* delay slot */
 }
 
-void bl_gen_jump_kernel(void **p,
+void bl_gen_jump_kernel(const MIPSCPU *cpu, void **p,
                         bool set_sp, target_ulong sp,
                         bool set_a0, target_ulong a0,
                         bool set_a1, target_ulong a1,
@@ -274,7 +274,7 @@ void bl_gen_jump_kernel(void **p,
         bl_gen_load_ulong(p, BL_REG_A3, a3);
     }
 
-    bl_gen_jump_to(p, kernel_addr);
+    bl_gen_jump_to(cpu, p, kernel_addr);
 }
 
 void bl_gen_write_ulong(const MIPSCPU *cpu, void **p,
diff --git a/hw/mips/boston.c b/hw/mips/boston.c
index b646c104df7..f2c0e335e73 100644
--- a/hw/mips/boston.c
+++ b/hw/mips/boston.c
@@ -353,7 +353,7 @@ static void gen_firmware(const MIPSCPU *cpu, void *p,
      * a2/$6 = 0
      * a3/$7 = 0
      */
-    bl_gen_jump_kernel(&p,
+    bl_gen_jump_kernel(cpu, &p,
                        true, 0, true, (int32_t)-2,
                        true, fdt_addr, true, 0, true, 0,
                        kernel_entry);
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index c4080a8a6e3..1e55adacdd2 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -179,7 +179,7 @@ static void write_bootloader(const MIPSCPU *cpu, uint8_t *base,
     /* Second part of the bootloader */
     p = (uint32_t *)(base + 0x040);
 
-    bl_gen_jump_kernel((void **)&p,
+    bl_gen_jump_kernel(cpu, (void **)&p,
                        true, ENVP_VADDR - 64,
                        true, 2, true, ENVP_VADDR,
                        true, ENVP_VADDR + 8,
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 9bc3fc9da3e..f96a78d2939 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -681,7 +681,7 @@ static void bl_setup_gt64120_jump_kernel(MaltaState *s, void **p,
                      cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc),
                      tswap32(ldl_be_p(pci_pins_cfg)));
 
-    bl_gen_jump_kernel(p,
+    bl_gen_jump_kernel(cpu, p,
                        true, ENVP_VADDR - 64,
                        /*
                         * If semihosting is used, arguments have already
-- 
2.47.1

[PATCH v2 12/19] hw/mips/bootloader: Propagate CPU env to bl_gen_load_ulong()

[Philippe Mathieu-Daudé]

Propagate the target specific CPU env to the locally
declared bl_gen_load_ulong() function.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 33 ++++++++++++++++++++++-----------
 1 file changed, 22 insertions(+), 11 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 9b074d9903b..198506431c5 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -233,7 +233,8 @@ static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm)
     bl_gen_ori(p, rt, rt, extract64(imm, 0, 16));
 }
 
-static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm)
+static void bl_gen_load_ulong(const CPUMIPSState *env, void **p,
+                              bl_reg rt, target_ulong imm)
 {
     if (bootcpu_supports_isa(ISA_MIPS3)) {
         bl_gen_dli(p, rt, imm); /* 64bit */
@@ -245,7 +246,9 @@ static void bl_gen_load_ulong(void **p, bl_reg rt, target_ulong imm)
 /* Helpers */
 void bl_gen_jump_to(const MIPSCPU *cpu, void **p, target_ulong jump_addr)
 {
-    bl_gen_load_ulong(p, BL_REG_T9, jump_addr);
+    const CPUMIPSState *env = &cpu->env;
+
+    bl_gen_load_ulong(env, p, BL_REG_T9, jump_addr);
     bl_gen_jalr(p, BL_REG_T9);
     bl_gen_nop(p); /* delay slot */
 }
@@ -258,20 +261,22 @@ void bl_gen_jump_kernel(const MIPSCPU *cpu, void **p,
                         bool set_a3, target_ulong a3,
                         target_ulong kernel_addr)
 {
+    const CPUMIPSState *env = &cpu->env;
+
     if (set_sp) {
-        bl_gen_load_ulong(p, BL_REG_SP, sp);
+        bl_gen_load_ulong(env, p, BL_REG_SP, sp);
     }
     if (set_a0) {
-        bl_gen_load_ulong(p, BL_REG_A0, a0);
+        bl_gen_load_ulong(env, p, BL_REG_A0, a0);
     }
     if (set_a1) {
-        bl_gen_load_ulong(p, BL_REG_A1, a1);
+        bl_gen_load_ulong(env, p, BL_REG_A1, a1);
     }
     if (set_a2) {
-        bl_gen_load_ulong(p, BL_REG_A2, a2);
+        bl_gen_load_ulong(env, p, BL_REG_A2, a2);
     }
     if (set_a3) {
-        bl_gen_load_ulong(p, BL_REG_A3, a3);
+        bl_gen_load_ulong(env, p, BL_REG_A3, a3);
     }
 
     bl_gen_jump_to(cpu, p, kernel_addr);
@@ -280,8 +285,10 @@ void bl_gen_jump_kernel(const MIPSCPU *cpu, void **p,
 void bl_gen_write_ulong(const MIPSCPU *cpu, void **p,
                         target_ulong addr, target_ulong val)
 {
-    bl_gen_load_ulong(p, BL_REG_K0, val);
-    bl_gen_load_ulong(p, BL_REG_K1, addr);
+    const CPUMIPSState *env = &cpu->env;
+
+    bl_gen_load_ulong(env, p, BL_REG_K0, val);
+    bl_gen_load_ulong(env, p, BL_REG_K1, addr);
     if (bootcpu_supports_isa(ISA_MIPS3)) {
         bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0);
     } else {
@@ -292,15 +299,19 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **p,
 void bl_gen_write_u32(const MIPSCPU *cpu, void **p,
                       target_ulong addr, uint32_t val)
 {
+    const CPUMIPSState *env = &cpu->env;
+
     bl_gen_li(p, BL_REG_K0, val);
-    bl_gen_load_ulong(p, BL_REG_K1, addr);
+    bl_gen_load_ulong(env, p, BL_REG_K1, addr);
     bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
 }
 
 void bl_gen_write_u64(const MIPSCPU *cpu, void **p,
                       target_ulong addr, uint64_t val)
 {
+    const CPUMIPSState *env = &cpu->env;
+
     bl_gen_dli(p, BL_REG_K0, val);
-    bl_gen_load_ulong(p, BL_REG_K1, addr);
+    bl_gen_load_ulong(env, p, BL_REG_K1, addr);
     bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0);
 }
-- 
2.47.1

[PATCH v2 13/19] hw/mips/bootloader: Propagate CPU env to bl_gen_[d]li()

[Philippe Mathieu-Daudé]

Propagate the target specific CPU env to the locally
declared bl_gen_li() and bl_gen_dli() functions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 198506431c5..464ed5f4f1a 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -213,7 +213,8 @@ static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
 }
 
 /* Pseudo instructions */
-static void bl_gen_li(void **p, bl_reg rt, uint32_t imm)
+static void bl_gen_li(const CPUMIPSState *env, void **p,
+                      bl_reg rt, uint32_t imm)
 {
     if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
         bl_gen_lui_nm(p, rt, extract32(imm, 12, 20));
@@ -224,9 +225,10 @@ static void bl_gen_li(void **p, bl_reg rt, uint32_t imm)
     }
 }
 
-static void bl_gen_dli(void **p, bl_reg rt, uint64_t imm)
+static void bl_gen_dli(const CPUMIPSState *env, void **p,
+                       bl_reg rt, uint64_t imm)
 {
-    bl_gen_li(p, rt, extract64(imm, 32, 32));
+    bl_gen_li(env, p, rt, extract64(imm, 32, 32));
     bl_gen_dsll(p, rt, rt, 16);
     bl_gen_ori(p, rt, rt, extract64(imm, 16, 16));
     bl_gen_dsll(p, rt, rt, 16);
@@ -237,9 +239,9 @@ static void bl_gen_load_ulong(const CPUMIPSState *env, void **p,
                               bl_reg rt, target_ulong imm)
 {
     if (bootcpu_supports_isa(ISA_MIPS3)) {
-        bl_gen_dli(p, rt, imm); /* 64bit */
+        bl_gen_dli(env, p, rt, imm); /* 64bit */
     } else {
-        bl_gen_li(p, rt, imm); /* 32bit */
+        bl_gen_li(env, p, rt, imm); /* 32bit */
     }
 }
 
@@ -301,7 +303,7 @@ void bl_gen_write_u32(const MIPSCPU *cpu, void **p,
 {
     const CPUMIPSState *env = &cpu->env;
 
-    bl_gen_li(p, BL_REG_K0, val);
+    bl_gen_li(env, p, BL_REG_K0, val);
     bl_gen_load_ulong(env, p, BL_REG_K1, addr);
     bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
 }
@@ -311,7 +313,7 @@ void bl_gen_write_u64(const MIPSCPU *cpu, void **p,
 {
     const CPUMIPSState *env = &cpu->env;
 
-    bl_gen_dli(p, BL_REG_K0, val);
+    bl_gen_dli(env, p, BL_REG_K0, val);
     bl_gen_load_ulong(env, p, BL_REG_K1, addr);
     bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0);
 }
-- 
2.47.1

[PATCH v2 14/19] hw/mips/bootloader: Propagate CPU env to bl_gen_s[w, d]()

[Philippe Mathieu-Daudé]

Propagate the target specific CPU env to the locally
declared bl_gen_sw() and bl_gen_sd() functions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 464ed5f4f1a..288dccce473 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -194,7 +194,8 @@ static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12)
     st_nm32_p(ptr, insn);
 }
 
-static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
+static void bl_gen_sw(const CPUMIPSState *env, void **p,
+                      bl_reg rt, uint8_t base, uint16_t offset)
 {
     if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
         bl_gen_sw_nm(p, rt, base, offset);
@@ -203,7 +204,8 @@ static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
     }
 }
 
-static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
+static void bl_gen_sd(const CPUMIPSState *env, void **p,
+                      bl_reg rt, uint8_t base, uint16_t offset)
 {
     if (bootcpu_supports_isa(ISA_MIPS3)) {
         bl_gen_i_type(p, 0x3f, base, rt, offset);
@@ -292,9 +294,9 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **p,
     bl_gen_load_ulong(env, p, BL_REG_K0, val);
     bl_gen_load_ulong(env, p, BL_REG_K1, addr);
     if (bootcpu_supports_isa(ISA_MIPS3)) {
-        bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0);
+        bl_gen_sd(env, p, BL_REG_K0, BL_REG_K1, 0x0);
     } else {
-        bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
+        bl_gen_sw(env, p, BL_REG_K0, BL_REG_K1, 0x0);
     }
 }
 
@@ -305,7 +307,7 @@ void bl_gen_write_u32(const MIPSCPU *cpu, void **p,
 
     bl_gen_li(env, p, BL_REG_K0, val);
     bl_gen_load_ulong(env, p, BL_REG_K1, addr);
-    bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0);
+    bl_gen_sw(env, p, BL_REG_K0, BL_REG_K1, 0x0);
 }
 
 void bl_gen_write_u64(const MIPSCPU *cpu, void **p,
@@ -315,5 +317,5 @@ void bl_gen_write_u64(const MIPSCPU *cpu, void **p,
 
     bl_gen_dli(env, p, BL_REG_K0, val);
     bl_gen_load_ulong(env, p, BL_REG_K1, addr);
-    bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0);
+    bl_gen_sd(env, p, BL_REG_K0, BL_REG_K1, 0x0);
 }
-- 
2.47.1

[PATCH v2 15/19] hw/mips/bootloader: Propagate CPU env to bl_gen_jalr()

[Philippe Mathieu-Daudé]

Propagate the target specific CPU env to the locally
declared bl_gen_jalr() function.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 288dccce473..a0fc840e89f 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -127,7 +127,7 @@ static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa)
     }
 }
 
-static void bl_gen_jalr(void **p, bl_reg rs)
+static void bl_gen_jalr(const CPUMIPSState *env, void **p, bl_reg rs)
 {
     if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
         uint32_t insn = 0;
@@ -253,7 +253,7 @@ void bl_gen_jump_to(const MIPSCPU *cpu, void **p, target_ulong jump_addr)
     const CPUMIPSState *env = &cpu->env;
 
     bl_gen_load_ulong(env, p, BL_REG_T9, jump_addr);
-    bl_gen_jalr(p, BL_REG_T9);
+    bl_gen_jalr(env, p, BL_REG_T9);
     bl_gen_nop(p); /* delay slot */
 }
 
-- 
2.47.1

[PATCH v2 16/19] hw/mips/bootloader: Propagate CPU env to bl_gen_dsll()

[Philippe Mathieu-Daudé]

Propagate the target specific CPU env to the locally
declared bl_gen_dsll() function.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index a0fc840e89f..e57d5c3278f 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -118,7 +118,8 @@ static void bl_gen_i_type(void **ptr, uint8_t opcode,
 }
 
 /* Single instructions */
-static void bl_gen_dsll(void **p, bl_reg rd, bl_reg rt, uint8_t sa)
+static void bl_gen_dsll(const CPUMIPSState *env, void **p,
+                        bl_reg rd, bl_reg rt, uint8_t sa)
 {
     if (bootcpu_supports_isa(ISA_MIPS3)) {
         bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
@@ -231,9 +232,9 @@ static void bl_gen_dli(const CPUMIPSState *env, void **p,
                        bl_reg rt, uint64_t imm)
 {
     bl_gen_li(env, p, rt, extract64(imm, 32, 32));
-    bl_gen_dsll(p, rt, rt, 16);
+    bl_gen_dsll(env, p, rt, rt, 16);
     bl_gen_ori(p, rt, rt, extract64(imm, 16, 16));
-    bl_gen_dsll(p, rt, rt, 16);
+    bl_gen_dsll(env, p, rt, rt, 16);
     bl_gen_ori(p, rt, rt, extract64(imm, 0, 16));
 }
 
-- 
2.47.1

[PATCH v2 17/19] hw/mips/bootloader: Propagate CPU env to bl_gen_nop()

[Philippe Mathieu-Daudé]

Propagate the target specific CPU env to the locally
declared bl_gen_nop() function.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index e57d5c3278f..a54af8160ef 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -67,7 +67,7 @@ static void st_nm32_p(void **ptr, uint32_t insn)
 }
 
 /* Base types */
-static void bl_gen_nop(void **ptr)
+static void bl_gen_nop(const CPUMIPSState *env, void **ptr)
 {
     if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
         st_nm32_p(ptr, 0x8000c000);
@@ -255,7 +255,7 @@ void bl_gen_jump_to(const MIPSCPU *cpu, void **p, target_ulong jump_addr)
 
     bl_gen_load_ulong(env, p, BL_REG_T9, jump_addr);
     bl_gen_jalr(env, p, BL_REG_T9);
-    bl_gen_nop(p); /* delay slot */
+    bl_gen_nop(env, p); /* delay slot */
 }
 
 void bl_gen_jump_kernel(const MIPSCPU *cpu, void **p,
-- 
2.47.1

[PATCH v2 18/19] hw/mips/bootloader: Propagate CPU env to bootcpu_supports_isa()

[Philippe Mathieu-Daudé]

Propagate the target specific CPU env to the locally
declared bootcpu_supports_isa() function.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index a54af8160ef..f02e5aabe48 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -49,7 +49,7 @@ typedef enum bl_reg {
     BL_REG_RA = 31,
 } bl_reg;
 
-static bool bootcpu_supports_isa(uint64_t isa_mask)
+static bool bootcpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask)
 {
     return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask);
 }
@@ -69,7 +69,7 @@ static void st_nm32_p(void **ptr, uint32_t insn)
 /* Base types */
 static void bl_gen_nop(const CPUMIPSState *env, void **ptr)
 {
-    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+    if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) {
         st_nm32_p(ptr, 0x8000c000);
     } else {
         uint32_t *p = *ptr;
@@ -121,7 +121,7 @@ static void bl_gen_i_type(void **ptr, uint8_t opcode,
 static void bl_gen_dsll(const CPUMIPSState *env, void **p,
                         bl_reg rd, bl_reg rt, uint8_t sa)
 {
-    if (bootcpu_supports_isa(ISA_MIPS3)) {
+    if (bootcpu_supports_isa(env, ISA_MIPS3)) {
         bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
     } else {
         g_assert_not_reached(); /* unsupported */
@@ -130,7 +130,7 @@ static void bl_gen_dsll(const CPUMIPSState *env, void **p,
 
 static void bl_gen_jalr(const CPUMIPSState *env, void **p, bl_reg rs)
 {
-    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+    if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) {
         uint32_t insn = 0;
 
         insn = deposit32(insn, 26, 6, 0b010010); /* JALRC */
@@ -198,7 +198,7 @@ static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12)
 static void bl_gen_sw(const CPUMIPSState *env, void **p,
                       bl_reg rt, uint8_t base, uint16_t offset)
 {
-    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+    if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) {
         bl_gen_sw_nm(p, rt, base, offset);
     } else {
         bl_gen_i_type(p, 0x2b, base, rt, offset);
@@ -208,7 +208,7 @@ static void bl_gen_sw(const CPUMIPSState *env, void **p,
 static void bl_gen_sd(const CPUMIPSState *env, void **p,
                       bl_reg rt, uint8_t base, uint16_t offset)
 {
-    if (bootcpu_supports_isa(ISA_MIPS3)) {
+    if (bootcpu_supports_isa(env, ISA_MIPS3)) {
         bl_gen_i_type(p, 0x3f, base, rt, offset);
     } else {
         g_assert_not_reached(); /* unsupported */
@@ -219,7 +219,7 @@ static void bl_gen_sd(const CPUMIPSState *env, void **p,
 static void bl_gen_li(const CPUMIPSState *env, void **p,
                       bl_reg rt, uint32_t imm)
 {
-    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+    if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) {
         bl_gen_lui_nm(p, rt, extract32(imm, 12, 20));
         bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12));
     } else {
@@ -241,7 +241,7 @@ static void bl_gen_dli(const CPUMIPSState *env, void **p,
 static void bl_gen_load_ulong(const CPUMIPSState *env, void **p,
                               bl_reg rt, target_ulong imm)
 {
-    if (bootcpu_supports_isa(ISA_MIPS3)) {
+    if (bootcpu_supports_isa(env, ISA_MIPS3)) {
         bl_gen_dli(env, p, rt, imm); /* 64bit */
     } else {
         bl_gen_li(env, p, rt, imm); /* 32bit */
@@ -294,7 +294,7 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **p,
 
     bl_gen_load_ulong(env, p, BL_REG_K0, val);
     bl_gen_load_ulong(env, p, BL_REG_K1, addr);
-    if (bootcpu_supports_isa(ISA_MIPS3)) {
+    if (bootcpu_supports_isa(env, ISA_MIPS3)) {
         bl_gen_sd(env, p, BL_REG_K0, BL_REG_K1, 0x0);
     } else {
         bl_gen_sw(env, p, BL_REG_K0, BL_REG_K1, 0x0);
-- 
2.47.1

[PATCH v2 19/19] hw/mips/bootloader: Remove use of &first_cpu in bootcpu_supports_isa()

[Philippe Mathieu-Daudé]

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/mips/bootloader.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index f02e5aabe48..1969610224d 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -51,7 +51,7 @@ typedef enum bl_reg {
 
 static bool bootcpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask)
 {
-    return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask);
+    return cpu_supports_isa(env, isa_mask);
 }
 
 static void st_nm32_p(void **ptr, uint32_t insn)
-- 
2.47.1

Re: [PATCH v2 00/19] hw/mips: Remove all uses of &first_cpu

[Jiaxun Yang]

在2025年1月13日一月 下午7:55，Philippe Mathieu-Daudé写道：
> v2:
> - Add documentation
> - Reorder propagation to reduce code churn around &first_cpu
>
> v1:
> - Keep references to vCPUs in CPS and MaltaState,
> - Refactor the MIPS Bootloader API to take CPU argument
> - Access first CPU propagate from machine_init()
>
> Based-on: <20250112215835.29320-1-philmd@linaro.org>
> "hw/mips/loongson3: Remove uses of &first_cpu global"

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Also tested bootloader stuff :-)

>
> Philippe Mathieu-Daudé (19):
>   hw/mips/cps: Keep reference of vCPUs in MIPSCPSState
>   hw/mips/malta: Check CPU index instead of using &first_cpu
>   hw/mips/malta: Keep reference of vCPUs in MaltaState
>   hw/mips/malta: Propagate MaltaState to write_bootloader()
>   hw/mips/malta: Propagate MaltaState to bl_setup_gt64120_jump_kernel()
>   hw/mips/boston: Replace bl_gen_write_ulong() -> bl_gen_write_u64()
>   hw/mips/boston: Propagate CPU to gen_firmware()
>   hw/mips/fuloong: Propagate CPU to write_bootloader()
>   hw/mips/bootloader: Document public API
>   hw/mips/bootloader: Propagate CPU to bl_gen_write_u[32,64,long]()
>   hw/mips/bootloader: Propagate CPU to bl_gen_jump_[to,kernel]()
>   hw/mips/bootloader: Propagate CPU env to bl_gen_load_ulong()
>   hw/mips/bootloader: Propagate CPU env to bl_gen_[d]li()
>   hw/mips/bootloader: Propagate CPU env to bl_gen_s[w,d]()
>   hw/mips/bootloader: Propagate CPU env to bl_gen_jalr()
>   hw/mips/bootloader: Propagate CPU env to bl_gen_dsll()
>   hw/mips/bootloader: Propagate CPU env to bl_gen_nop()
>   hw/mips/bootloader: Propagate CPU env to bootcpu_supports_isa()
>   hw/mips/bootloader: Remove use of &first_cpu in bootcpu_supports_isa()
>
>  include/hw/mips/bootloader.h |  69 +++++++++++++++++++--
>  include/hw/mips/cps.h        |   1 +
>  hw/mips/bootloader.c         | 113 ++++++++++++++++++++---------------
>  hw/mips/boston.c             |  21 ++++---
>  hw/mips/cps.c                |   4 +-
>  hw/mips/fuloong2e.c          |   6 +-
>  hw/mips/malta.c              |  60 +++++++++++--------
>  7 files changed, 184 insertions(+), 90 deletions(-)
>
> -- 
> 2.47.1

-- 
- Jiaxun