Re: [PATCH v2] hw/riscv: Add Microblaze V 32bit virt board

[Michal Simek <michal.simek@amd.com>]

Hi Alistair,

On 10/30/24 03:54, Alistair Francis wrote:
> On Thu, Oct 17, 2024 at 5:26 PM Sai Pavan Boddu <sai.pavan.boddu@amd.com> wrote:

>> diff --git a/hw/riscv/microblaze-v-virt.c b/hw/riscv/microblaze-v-virt.c
>> new file mode 100644
>> index 00000000000..6603e6d6b06
>> --- /dev/null
>> +++ b/hw/riscv/microblaze-v-virt.c
>> @@ -0,0 +1,181 @@
>> +/*
>> + * QEMU model of Microblaze V (32bit version)
>> + *
>> + * based on hw/microblaze/petalogix_ml605_mmu.c
> 
> Just a question, are you sure the virt board should be based on the
> petalogix_ml605_mmu?

It is definitely based on ml605 and it is fair to say it and keep origin 
copyrights around.

> This will be the reference Microblaze V implementation in QEMU, and
> the petalogix_ml605_mmu might be a bit old now. It also uses a lot of
> the Microblaze architecture components (like the interrupt controller)
> compared to the RISC-V architecture components which might cause
> issues for you in the future.
> 
> Just something to keep in mind

And the reason is that it is really design like that in design tool (Vivado).
There is no risc-v specific interrupt controller use but origin axi intc used in 
origin Microblaze designs. Timer is the same story.

ml605 board and it's chip is old but IPs which are used are still supported and 
used in new designs.

And regarding using virt in name. We can create design like it is described but 
it is not going to work on standard evaluation boards without extra fmc cards 
for example.
It means word virt is just description that it is not really target any specific 
board. Definitely name can change and suggestions are welcome.

Thanks,
Michal