From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Sricharan R <quic_srichara@quicinc.com>,
andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
konradybcio@kernel.org, rafael@kernel.org,
viresh.kumar@linaro.org, ilia.lin@kernel.org,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org
Subject: Re: [PATCH 3/4] cpufreq: qcom-nvmem: Enable cpufreq for ipq5424
Date: Mon, 27 Jan 2025 16:12:05 +0100 [thread overview]
Message-ID: <7e118726-b22b-4c7b-9966-07c3b1ff709c@oss.qualcomm.com> (raw)
In-Reply-To: <20250127093128.2611247-4-quic_srichara@quicinc.com>
On 27.01.2025 10:31 AM, Sricharan R wrote:
> From: Md Sadre Alam <quic_mdalam@quicinc.com>
>
> IPQ5424 have different OPPs available for the CPU based on
> SoC variant. This can be determined through use of an eFuse
> register present in the silicon.
>
> Added support for ipq5424 on nvmem driver which helps to
> determine OPPs at runtime based on the eFuse register which
> has the CPU frequency limits. opp-supported-hw dt binding
> can be used to indicate the available OPPs for each limit.
>
> nvmem driver also creates the "cpufreq-dt" platform_device after
> passing the version matching data to the OPP framework so that the
> cpufreq-dt handles the actual cpufreq implementation.
>
> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
> ---
> drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
> drivers/cpufreq/qcom-cpufreq-nvmem.c | 5 +++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index 9c198bd4f7e9..4045bc3ce805 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -187,6 +187,7 @@ static const struct of_device_id blocklist[] __initconst = {
> { .compatible = "ti,am62p5", },
>
> { .compatible = "qcom,ipq5332", },
> + { .compatible = "qcom,ipq5424", },
> { .compatible = "qcom,ipq6018", },
> { .compatible = "qcom,ipq8064", },
> { .compatible = "qcom,ipq8074", },
> diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> index 3a8ed723a23e..102f7f1b031c 100644
> --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c
> +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c
> @@ -200,6 +200,10 @@ static int qcom_cpufreq_kryo_name_version(struct device *cpu_dev,
> case QCOM_ID_IPQ9574:
> drv->versions = 1 << (unsigned int)(*speedbin);
> break;
> + case QCOM_ID_IPQ5424:
> + case QCOM_ID_IPQ5404:
> + drv->versions = (*speedbin != 0x3b) ? BIT(0) : BIT(1);
Perhaps:
drv->versions = (*speedbin == 0x3b) ? BIT(1) : BIT(0);
But ultimately both work:
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
next prev parent reply other threads:[~2025-01-27 15:12 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-27 9:31 [PATCH 0/4] Enable cpufreq for IPQ5424 Sricharan R
2025-01-27 9:31 ` [PATCH 1/4] dt-bindings: clock: ipq5424-apss-clk: Add ipq5424 apss clock controller Sricharan R
2025-01-28 7:34 ` Krzysztof Kozlowski
2025-01-28 11:15 ` Sricharan Ramabadhran
2025-01-28 12:30 ` Krzysztof Kozlowski
2025-01-30 10:39 ` Sricharan Ramabadhran
2025-02-01 15:21 ` Konrad Dybcio
2025-02-02 14:38 ` Krzysztof Kozlowski
2025-01-27 9:31 ` [PATCH 2/4] clk: qcom: apss-ipq5424: " Sricharan R
2025-01-28 7:48 ` Varadarajan Narayanan
2025-01-29 11:39 ` Sricharan Ramabadhran
2025-01-28 11:59 ` Konrad Dybcio
2025-01-30 10:03 ` Sricharan Ramabadhran
2025-02-01 15:25 ` Konrad Dybcio
2025-02-04 6:28 ` Sricharan Ramabadhran
2025-02-10 19:14 ` Konrad Dybcio
2025-01-27 9:31 ` [PATCH 3/4] cpufreq: qcom-nvmem: Enable cpufreq for ipq5424 Sricharan R
2025-01-27 15:12 ` Konrad Dybcio [this message]
2025-01-27 9:31 ` [PATCH 4/4] arm64: dts: qcom: ipq5424: Enable cpufreq support Sricharan R
2025-03-08 18:18 ` Konrad Dybcio
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