From: Damon Ding <damon.ding@rock-chips.com>
To: "Nicolas Frattaroli" <nicolas.frattaroli@collabora.com>,
"Uwe Kleine-König" <ukleinek@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Heiko Stuebner" <heiko@sntech.de>, "Lee Jones" <lee@kernel.org>,
"William Breathitt Gray" <wbg@kernel.org>
Cc: kernel@collabora.com, Jonas Karlman <jonas@kwiboo.se>,
Alexey Charkov <alchark@gmail.com>,
linux-rockchip@lists.infradead.org, linux-pwm@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org
Subject: Re: [PATCH v5 5/6] arm64: dts: rockchip: add PWM nodes to RK3576 SoC dtsi
Date: Sun, 26 Apr 2026 15:30:35 +0800 [thread overview]
Message-ID: <7e55f270-5422-4696-987d-e2a2ab16240b@rock-chips.com> (raw)
In-Reply-To: <20260420-rk3576-pwm-v5-5-ae7cfbbe5427@collabora.com>
Hi Nicolas,
On 4/20/2026 9:52 PM, Nicolas Frattaroli wrote:
> The RK3576 SoC features three distinct PWM controllers, with variable
> numbers of channels. Add each channel as a separate node to the SoC's
> device tree, as they don't really overlap in register ranges.
>
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3576.dtsi | 208 +++++++++++++++++++++++++++++++
> 1 file changed, 208 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> index e12a2a0cfb89..55d6b103c329 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> @@ -1032,6 +1032,32 @@ uart1: serial@27310000 {
> status = "disabled";
> };
>
> + pwm0_2ch_0: pwm@27330000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x27330000 0x0 0x1000>;
> + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>,
> + <&cru CLK_PMU1PWM_OSC>, <&cru CLK_PMU1PWM_RC>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm0m0_ch0>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm0_2ch_1: pwm@27331000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x27331000 0x0 0x1000>;
> + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>,
> + <&cru CLK_PMU1PWM_OSC>, <&cru CLK_PMU1PWM_RC>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm0m0_ch1>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> pmu: power-management@27380000 {
> compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd";
> reg = <0x0 0x27380000 0x0 0x800>;
> @@ -2630,6 +2656,188 @@ uart9: serial@2adc0000 {
> status = "disabled";
> };
>
> + pwm1_6ch_0: pwm@2add0000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add0000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch0>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_1: pwm@2add1000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add1000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch1>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_2: pwm@2add2000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add2000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch2>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_3: pwm@2add3000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add3000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch3>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_4: pwm@2add4000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add4000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch4>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_5: pwm@2add5000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add5000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch5>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_0: pwm@2ade0000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade0000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch0>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_1: pwm@2ade1000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade1000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch1>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_2: pwm@2ade2000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade2000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch2>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_3: pwm@2ade3000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade3000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch3>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_4: pwm@2ade4000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade4000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch4>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_5: pwm@2ade5000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade5000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch5>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_6: pwm@2ade6000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade6000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch6>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_7: pwm@2ade7000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade7000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch7>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> saradc: adc@2ae00000 {
> compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc";
> reg = <0x0 0x2ae00000 0x0 0x10000>;
>
According to the RK3576 TRM, the register base address, clocks and
interrupt configuration of the PWM node are all correct
Reviewed-by: Damon Ding <damon.ding@rock-chips.com>
Best regards,
Damon
WARNING: multiple messages have this Message-ID (diff)
From: Damon Ding <damon.ding@rock-chips.com>
To: "Nicolas Frattaroli" <nicolas.frattaroli@collabora.com>,
"Uwe Kleine-König" <ukleinek@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Heiko Stuebner" <heiko@sntech.de>, "Lee Jones" <lee@kernel.org>,
"William Breathitt Gray" <wbg@kernel.org>
Cc: kernel@collabora.com, Jonas Karlman <jonas@kwiboo.se>,
Alexey Charkov <alchark@gmail.com>,
linux-rockchip@lists.infradead.org, linux-pwm@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org
Subject: Re: [PATCH v5 5/6] arm64: dts: rockchip: add PWM nodes to RK3576 SoC dtsi
Date: Sun, 26 Apr 2026 15:30:35 +0800 [thread overview]
Message-ID: <7e55f270-5422-4696-987d-e2a2ab16240b@rock-chips.com> (raw)
In-Reply-To: <20260420-rk3576-pwm-v5-5-ae7cfbbe5427@collabora.com>
Hi Nicolas,
On 4/20/2026 9:52 PM, Nicolas Frattaroli wrote:
> The RK3576 SoC features three distinct PWM controllers, with variable
> numbers of channels. Add each channel as a separate node to the SoC's
> device tree, as they don't really overlap in register ranges.
>
> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> ---
> arch/arm64/boot/dts/rockchip/rk3576.dtsi | 208 +++++++++++++++++++++++++++++++
> 1 file changed, 208 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> index e12a2a0cfb89..55d6b103c329 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> @@ -1032,6 +1032,32 @@ uart1: serial@27310000 {
> status = "disabled";
> };
>
> + pwm0_2ch_0: pwm@27330000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x27330000 0x0 0x1000>;
> + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>,
> + <&cru CLK_PMU1PWM_OSC>, <&cru CLK_PMU1PWM_RC>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm0m0_ch0>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm0_2ch_1: pwm@27331000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x27331000 0x0 0x1000>;
> + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>,
> + <&cru CLK_PMU1PWM_OSC>, <&cru CLK_PMU1PWM_RC>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm0m0_ch1>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> pmu: power-management@27380000 {
> compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd";
> reg = <0x0 0x27380000 0x0 0x800>;
> @@ -2630,6 +2656,188 @@ uart9: serial@2adc0000 {
> status = "disabled";
> };
>
> + pwm1_6ch_0: pwm@2add0000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add0000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch0>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_1: pwm@2add1000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add1000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch1>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_2: pwm@2add2000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add2000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch2>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_3: pwm@2add3000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add3000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch3>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_4: pwm@2add4000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add4000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch4>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm1_6ch_5: pwm@2add5000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2add5000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>,
> + <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm1m0_ch5>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_0: pwm@2ade0000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade0000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch0>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_1: pwm@2ade1000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade1000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch1>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_2: pwm@2ade2000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade2000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch2>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_3: pwm@2ade3000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade3000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch3>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_4: pwm@2ade4000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade4000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch4>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_5: pwm@2ade5000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade5000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch5>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_6: pwm@2ade6000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade6000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch6>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + pwm2_8ch_7: pwm@2ade7000 {
> + compatible = "rockchip,rk3576-pwm";
> + reg = <0x0 0x2ade7000 0x0 0x1000>;
> + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>,
> + <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>;
> + clock-names = "pwm", "pclk", "osc", "rc";
> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm2m0_ch7>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> saradc: adc@2ae00000 {
> compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc";
> reg = <0x0 0x2ae00000 0x0 0x10000>;
>
According to the RK3576 TRM, the register base address, clocks and
interrupt configuration of the PWM node are all correct
Reviewed-by: Damon Ding <damon.ding@rock-chips.com>
Best regards,
Damon
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2026-04-26 7:30 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-20 13:52 [PATCH v5 0/6] Add Rockchip RK3576 PWM Support Through MFPWM Nicolas Frattaroli
2026-04-20 13:52 ` Nicolas Frattaroli
2026-04-20 13:52 ` [PATCH v5 1/6] dt-bindings: pwm: Add a new binding for rockchip,rk3576-pwm Nicolas Frattaroli
2026-04-20 13:52 ` Nicolas Frattaroli
2026-04-20 13:52 ` [PATCH v5 2/6] mfd: Add Rockchip mfpwm driver Nicolas Frattaroli
2026-04-20 13:52 ` Nicolas Frattaroli
2026-05-14 11:41 ` Lee Jones
2026-05-14 11:41 ` Lee Jones
2026-04-20 13:52 ` [PATCH v5 3/6] pwm: Add rockchip PWMv4 driver Nicolas Frattaroli
2026-04-20 13:52 ` Nicolas Frattaroli
2026-04-26 9:44 ` Damon Ding
2026-04-26 9:44 ` Damon Ding
2026-04-26 13:06 ` Uwe Kleine-König
2026-04-26 13:06 ` Uwe Kleine-König
2026-04-27 1:20 ` Damon Ding
2026-04-27 1:20 ` Damon Ding
2026-04-26 10:09 ` Damon Ding
2026-04-26 10:09 ` Damon Ding
2026-04-20 13:52 ` [PATCH v5 4/6] counter: Add rockchip-pwm-capture driver Nicolas Frattaroli
2026-04-20 13:52 ` Nicolas Frattaroli
2026-04-26 10:55 ` Damon Ding
2026-04-26 10:55 ` Damon Ding
2026-04-27 17:35 ` Nicolas Frattaroli
2026-04-27 17:35 ` Nicolas Frattaroli
2026-05-03 11:06 ` William Breathitt Gray
2026-05-03 11:06 ` William Breathitt Gray
2026-05-03 10:46 ` William Breathitt Gray
2026-05-03 10:46 ` William Breathitt Gray
2026-05-04 8:25 ` Nicolas Frattaroli
2026-05-04 8:25 ` Nicolas Frattaroli
2026-04-20 13:52 ` [PATCH v5 5/6] arm64: dts: rockchip: add PWM nodes to RK3576 SoC dtsi Nicolas Frattaroli
2026-04-20 13:52 ` Nicolas Frattaroli
2026-04-26 7:30 ` Damon Ding [this message]
2026-04-26 7:30 ` Damon Ding
2026-04-20 13:52 ` [PATCH v5 6/6] arm64: dts: rockchip: Add cooling fan to ROCK 4D Nicolas Frattaroli
2026-04-20 13:52 ` Nicolas Frattaroli
2026-04-26 7:23 ` Damon Ding
2026-04-26 7:23 ` Damon Ding
2026-04-27 17:17 ` Nicolas Frattaroli
2026-04-27 17:17 ` Nicolas Frattaroli
2026-04-21 15:56 ` [PATCH v5 0/6] Add Rockchip RK3576 PWM Support Through MFPWM Jonathan Cameron
2026-04-21 15:56 ` Jonathan Cameron
2026-04-22 11:31 ` Nicolas Frattaroli
2026-04-22 11:31 ` Nicolas Frattaroli
2026-04-24 10:43 ` Uwe Kleine-König
2026-04-24 10:43 ` Uwe Kleine-König
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=7e55f270-5422-4696-987d-e2a2ab16240b@rock-chips.com \
--to=damon.ding@rock-chips.com \
--cc=alchark@gmail.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=heiko@sntech.de \
--cc=jonas@kwiboo.se \
--cc=kernel@collabora.com \
--cc=krzk+dt@kernel.org \
--cc=lee@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-iio@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pwm@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=nicolas.frattaroli@collabora.com \
--cc=robh@kernel.org \
--cc=ukleinek@kernel.org \
--cc=wbg@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.