From: khilman@baylibre.com (Kevin Hilman)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 08/14] mmc: meson-gx: rework clock init function
Date: Mon, 07 Aug 2017 14:34:06 -0700 [thread overview]
Message-ID: <7h4ltjoyep.fsf@baylibre.com> (raw)
In-Reply-To: <20170804174353.16486-9-jbrunet@baylibre.com> (Jerome Brunet's message of "Fri, 4 Aug 2017 19:43:47 +0200")
Jerome Brunet <jbrunet@baylibre.com> writes:
> Perform basic initialisation of the clk register before providing it to
> the CCF.
>
> Thanks to devm, carrying the clock structure around after init is not
> necessary. Rework the function to remove these from the controller host
> data.
>
> Finally, set initial mmc clock rate before enabling it, simplifying the
> exit condition.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
> drivers/mmc/host/meson-gx-mmc.c | 101 +++++++++++++++++++---------------------
> 1 file changed, 49 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
> index 8f9ba5190c18..4cc7d6530536 100644
> --- a/drivers/mmc/host/meson-gx-mmc.c
> +++ b/drivers/mmc/host/meson-gx-mmc.c
> @@ -42,10 +42,7 @@
>
> #define SD_EMMC_CLOCK 0x0
> #define CLK_DIV_MASK GENMASK(5, 0)
> -#define CLK_DIV_MAX 63
> #define CLK_SRC_MASK GENMASK(7, 6)
> -#define CLK_SRC_XTAL 0 /* external crystal */
> -#define CLK_SRC_PLL 1 /* FCLK_DIV2 */
> #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
> #define CLK_TX_PHASE_MASK GENMASK(11, 10)
> #define CLK_RX_PHASE_MASK GENMASK(13, 12)
> @@ -137,13 +134,9 @@ struct meson_host {
> spinlock_t lock;
> void __iomem *regs;
> struct clk *core_clk;
> - struct clk_mux mux;
> - struct clk *mux_clk;
> + struct clk *signal_clk;
> unsigned long req_rate;
>
> - struct clk_divider cfg_div;
> - struct clk *cfg_div_clk;
> -
> unsigned int bounce_buf_size;
> void *bounce_buf;
> dma_addr_t bounce_dma_addr;
> @@ -291,7 +284,7 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate)
> return 0;
> }
>
> - ret = clk_set_rate(host->cfg_div_clk, clk_rate);
> + ret = clk_set_rate(host->signal_clk, clk_rate);
minor nit: where does the name "signal" come from? I called this
"div_clk" because it's the output of the divider right before the
sd/emmc IP block. Admittedly, that's not a great name either, and I'm
not too picky about the naming, just curious...
Looking at the diagram we have since I initially wrote the driver, this
is more commonly referred to as device_clk.
Anyways, if you're going to rename...
[...]
> static void meson_mmc_set_tuning_params(struct mmc_host *mmc)
> @@ -987,7 +984,7 @@ static int meson_mmc_probe(struct platform_device *pdev)
> dma_free_coherent(host->dev, host->bounce_buf_size,
> host->bounce_buf, host->bounce_dma_addr);
> err_div_clk:
... probably should rename this too.
Otherwise,
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Kevin
WARNING: multiple messages have this Message-ID (diff)
From: Kevin Hilman <khilman@baylibre.com>
To: Jerome Brunet <jbrunet@baylibre.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>,
Carlo Caione <carlo@caione.org>,
linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 08/14] mmc: meson-gx: rework clock init function
Date: Mon, 07 Aug 2017 14:34:06 -0700 [thread overview]
Message-ID: <7h4ltjoyep.fsf@baylibre.com> (raw)
In-Reply-To: <20170804174353.16486-9-jbrunet@baylibre.com> (Jerome Brunet's message of "Fri, 4 Aug 2017 19:43:47 +0200")
Jerome Brunet <jbrunet@baylibre.com> writes:
> Perform basic initialisation of the clk register before providing it to
> the CCF.
>
> Thanks to devm, carrying the clock structure around after init is not
> necessary. Rework the function to remove these from the controller host
> data.
>
> Finally, set initial mmc clock rate before enabling it, simplifying the
> exit condition.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
> drivers/mmc/host/meson-gx-mmc.c | 101 +++++++++++++++++++---------------------
> 1 file changed, 49 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
> index 8f9ba5190c18..4cc7d6530536 100644
> --- a/drivers/mmc/host/meson-gx-mmc.c
> +++ b/drivers/mmc/host/meson-gx-mmc.c
> @@ -42,10 +42,7 @@
>
> #define SD_EMMC_CLOCK 0x0
> #define CLK_DIV_MASK GENMASK(5, 0)
> -#define CLK_DIV_MAX 63
> #define CLK_SRC_MASK GENMASK(7, 6)
> -#define CLK_SRC_XTAL 0 /* external crystal */
> -#define CLK_SRC_PLL 1 /* FCLK_DIV2 */
> #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
> #define CLK_TX_PHASE_MASK GENMASK(11, 10)
> #define CLK_RX_PHASE_MASK GENMASK(13, 12)
> @@ -137,13 +134,9 @@ struct meson_host {
> spinlock_t lock;
> void __iomem *regs;
> struct clk *core_clk;
> - struct clk_mux mux;
> - struct clk *mux_clk;
> + struct clk *signal_clk;
> unsigned long req_rate;
>
> - struct clk_divider cfg_div;
> - struct clk *cfg_div_clk;
> -
> unsigned int bounce_buf_size;
> void *bounce_buf;
> dma_addr_t bounce_dma_addr;
> @@ -291,7 +284,7 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate)
> return 0;
> }
>
> - ret = clk_set_rate(host->cfg_div_clk, clk_rate);
> + ret = clk_set_rate(host->signal_clk, clk_rate);
minor nit: where does the name "signal" come from? I called this
"div_clk" because it's the output of the divider right before the
sd/emmc IP block. Admittedly, that's not a great name either, and I'm
not too picky about the naming, just curious...
Looking at the diagram we have since I initially wrote the driver, this
is more commonly referred to as device_clk.
Anyways, if you're going to rename...
[...]
> static void meson_mmc_set_tuning_params(struct mmc_host *mmc)
> @@ -987,7 +984,7 @@ static int meson_mmc_probe(struct platform_device *pdev)
> dma_free_coherent(host->dev, host->bounce_buf_size,
> host->bounce_buf, host->bounce_dma_addr);
> err_div_clk:
... probably should rename this too.
Otherwise,
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Kevin
WARNING: multiple messages have this Message-ID (diff)
From: khilman@baylibre.com (Kevin Hilman)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 08/14] mmc: meson-gx: rework clock init function
Date: Mon, 07 Aug 2017 14:34:06 -0700 [thread overview]
Message-ID: <7h4ltjoyep.fsf@baylibre.com> (raw)
In-Reply-To: <20170804174353.16486-9-jbrunet@baylibre.com> (Jerome Brunet's message of "Fri, 4 Aug 2017 19:43:47 +0200")
Jerome Brunet <jbrunet@baylibre.com> writes:
> Perform basic initialisation of the clk register before providing it to
> the CCF.
>
> Thanks to devm, carrying the clock structure around after init is not
> necessary. Rework the function to remove these from the controller host
> data.
>
> Finally, set initial mmc clock rate before enabling it, simplifying the
> exit condition.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
> drivers/mmc/host/meson-gx-mmc.c | 101 +++++++++++++++++++---------------------
> 1 file changed, 49 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
> index 8f9ba5190c18..4cc7d6530536 100644
> --- a/drivers/mmc/host/meson-gx-mmc.c
> +++ b/drivers/mmc/host/meson-gx-mmc.c
> @@ -42,10 +42,7 @@
>
> #define SD_EMMC_CLOCK 0x0
> #define CLK_DIV_MASK GENMASK(5, 0)
> -#define CLK_DIV_MAX 63
> #define CLK_SRC_MASK GENMASK(7, 6)
> -#define CLK_SRC_XTAL 0 /* external crystal */
> -#define CLK_SRC_PLL 1 /* FCLK_DIV2 */
> #define CLK_CORE_PHASE_MASK GENMASK(9, 8)
> #define CLK_TX_PHASE_MASK GENMASK(11, 10)
> #define CLK_RX_PHASE_MASK GENMASK(13, 12)
> @@ -137,13 +134,9 @@ struct meson_host {
> spinlock_t lock;
> void __iomem *regs;
> struct clk *core_clk;
> - struct clk_mux mux;
> - struct clk *mux_clk;
> + struct clk *signal_clk;
> unsigned long req_rate;
>
> - struct clk_divider cfg_div;
> - struct clk *cfg_div_clk;
> -
> unsigned int bounce_buf_size;
> void *bounce_buf;
> dma_addr_t bounce_dma_addr;
> @@ -291,7 +284,7 @@ static int meson_mmc_clk_set(struct meson_host *host, unsigned long clk_rate)
> return 0;
> }
>
> - ret = clk_set_rate(host->cfg_div_clk, clk_rate);
> + ret = clk_set_rate(host->signal_clk, clk_rate);
minor nit: where does the name "signal" come from? I called this
"div_clk" because it's the output of the divider right before the
sd/emmc IP block. Admittedly, that's not a great name either, and I'm
not too picky about the naming, just curious...
Looking at the diagram we have since I initially wrote the driver, this
is more commonly referred to as device_clk.
Anyways, if you're going to rename...
[...]
> static void meson_mmc_set_tuning_params(struct mmc_host *mmc)
> @@ -987,7 +984,7 @@ static int meson_mmc_probe(struct platform_device *pdev)
> dma_free_coherent(host->dev, host->bounce_buf_size,
> host->bounce_buf, host->bounce_dma_addr);
> err_div_clk:
... probably should rename this too.
Otherwise,
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Kevin
next prev parent reply other threads:[~2017-08-07 21:34 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-04 17:43 [PATCH 00/14] mmc: meson-gx: driver fixups and upgrade Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` [PATCH 01/14] mmc: meson-gx: fix mux mask definition Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` [PATCH 02/14] mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flag Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` [PATCH 03/14] mmc: meson-gx: clean up some constants Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-07 21:06 ` Kevin Hilman
2017-08-07 21:06 ` Kevin Hilman
2017-08-07 21:06 ` Kevin Hilman
2017-08-21 11:54 ` Jerome Brunet
2017-08-21 11:54 ` Jerome Brunet
2017-08-21 11:54 ` Jerome Brunet
2017-08-04 17:43 ` [PATCH 04/14] mmc: meson-gx: use _irqsave variant of spinlock Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` [PATCH 05/14] mmc: meson-gx: cfg init overwrite values Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` [PATCH 06/14] mmc: meson-gx: rework set_ios function Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` [PATCH 07/14] mmc: meson-gx: rework clk_set function Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` [PATCH 08/14] mmc: meson-gx: rework clock init function Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-07 21:34 ` Kevin Hilman [this message]
2017-08-07 21:34 ` Kevin Hilman
2017-08-07 21:34 ` Kevin Hilman
2017-08-21 12:05 ` Jerome Brunet
2017-08-21 12:05 ` Jerome Brunet
2017-08-21 12:05 ` Jerome Brunet
2017-08-04 17:43 ` [PATCH 09/14] mmc: meson-gx: simplify interrupt handler Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` [PATCH 10/14] mmc: meson-gx: implement card_busy callback Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` [PATCH 11/14] mmc: meson-gx: rework tuning function Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` [PATCH 12/14] mmc: meson-gx: fix dual data rate mode frequencies Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` [PATCH 13/14] mmc: meson-gx: work around clk-stop issue Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-07 21:41 ` Kevin Hilman
2017-08-07 21:41 ` Kevin Hilman
2017-08-07 21:41 ` Kevin Hilman
2017-08-04 17:43 ` [PATCH 14/14] mmc: meson-gx: implement voltage switch callback Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-04 17:43 ` Jerome Brunet
2017-08-07 16:48 ` [PATCH 00/14] mmc: meson-gx: driver fixups and upgrade Jerome Brunet
2017-08-07 16:48 ` Jerome Brunet
2017-08-07 16:48 ` Jerome Brunet
2017-08-07 21:44 ` Kevin Hilman
2017-08-07 21:44 ` Kevin Hilman
2017-08-07 21:44 ` Kevin Hilman
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