From: khilman@baylibre.com (Kevin Hilman)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver
Date: Mon, 17 Oct 2016 09:54:15 -0700 [thread overview]
Message-ID: <7h8ttmdih4.fsf@baylibre.com> (raw)
In-Reply-To: <1476721850-454-2-git-send-email-bgolaszewski@baylibre.com> (Bartosz Golaszewski's message of "Mon, 17 Oct 2016 18:30:48 +0200")
Bartosz Golaszewski <bgolaszewski@baylibre.com> writes:
> Create a new driver for the da8xx DDR2/mDDR controller and implement
> support for writing to the Peripheral Bus Burst Priority Register.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
[...]
> diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
> new file mode 100644
> index 0000000..dcd0a61
> --- /dev/null
> +++ b/drivers/memory/da8xx-ddrctl.c
> @@ -0,0 +1,77 @@
> +/*
> + * TI da8xx DDR2/mDDR controller driver
> + *
> + * Copyright (C) 2016 BayLibre SAS
> + *
> + * Author:
> + * Bartosz Golaszewski <bgolaszewski@baylibre.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define DA8XX_DDR_CTL_BASE 0xB0000000
This base addr should be the reg property of the node.
> +#define DA8XX_PBBPR_OFFSET 0x00000020
> +#define DA8XX_PBBPR_REG(p) ((p) + DA8XX_PBBPR_OFFSET)
Kevin
WARNING: multiple messages have this Message-ID (diff)
From: Kevin Hilman <khilman@baylibre.com>
To: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
linux-devicetree <devicetree@vger.kernel.org>,
Tomi Valkeinen <tomi.valkeinen@ti.com>,
Michael Turquette <mturquette@baylibre.com>,
Sekhar Nori <nsekhar@ti.com>,
Russell King <linux@armlinux.org.uk>,
linux-drm <dri-devel@lists.freedesktop.org>,
LKML <linux-kernel@vger.kernel.org>,
Peter Ujfalusi <peter.ujfalusi@ti.com>,
Rob Herring <robh+dt@kernel.org>, Jyri Sarha <jsarha@ti.com>,
Frank Rowand <frowand.list@gmail.com>,
arm-soc <linux-arm-kernel@lists.infradead.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Subject: Re: [PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver
Date: Mon, 17 Oct 2016 09:54:15 -0700 [thread overview]
Message-ID: <7h8ttmdih4.fsf@baylibre.com> (raw)
In-Reply-To: <1476721850-454-2-git-send-email-bgolaszewski@baylibre.com> (Bartosz Golaszewski's message of "Mon, 17 Oct 2016 18:30:48 +0200")
Bartosz Golaszewski <bgolaszewski@baylibre.com> writes:
> Create a new driver for the da8xx DDR2/mDDR controller and implement
> support for writing to the Peripheral Bus Burst Priority Register.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
[...]
> diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
> new file mode 100644
> index 0000000..dcd0a61
> --- /dev/null
> +++ b/drivers/memory/da8xx-ddrctl.c
> @@ -0,0 +1,77 @@
> +/*
> + * TI da8xx DDR2/mDDR controller driver
> + *
> + * Copyright (C) 2016 BayLibre SAS
> + *
> + * Author:
> + * Bartosz Golaszewski <bgolaszewski@baylibre.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define DA8XX_DDR_CTL_BASE 0xB0000000
This base addr should be the reg property of the node.
> +#define DA8XX_PBBPR_OFFSET 0x00000020
> +#define DA8XX_PBBPR_REG(p) ((p) + DA8XX_PBBPR_OFFSET)
Kevin
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dri-devel@lists.freedesktop.org
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WARNING: multiple messages have this Message-ID (diff)
From: Kevin Hilman <khilman@baylibre.com>
To: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Sekhar Nori <nsekhar@ti.com>, Rob Herring <robh+dt@kernel.org>,
Frank Rowand <frowand.list@gmail.com>,
Mark Rutland <mark.rutland@arm.com>,
Peter Ujfalusi <peter.ujfalusi@ti.com>,
Russell King <linux@armlinux.org.uk>,
LKML <linux-kernel@vger.kernel.org>,
arm-soc <linux-arm-kernel@lists.infradead.org>,
linux-drm <dri-devel@lists.freedesktop.org>,
linux-devicetree <devicetree@vger.kernel.org>,
Jyri Sarha <jsarha@ti.com>,
Tomi Valkeinen <tomi.valkeinen@ti.com>,
David Airlie <airlied@linux.ie>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Subject: Re: [PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver
Date: Mon, 17 Oct 2016 09:54:15 -0700 [thread overview]
Message-ID: <7h8ttmdih4.fsf@baylibre.com> (raw)
In-Reply-To: <1476721850-454-2-git-send-email-bgolaszewski@baylibre.com> (Bartosz Golaszewski's message of "Mon, 17 Oct 2016 18:30:48 +0200")
Bartosz Golaszewski <bgolaszewski@baylibre.com> writes:
> Create a new driver for the da8xx DDR2/mDDR controller and implement
> support for writing to the Peripheral Bus Burst Priority Register.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
[...]
> diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c
> new file mode 100644
> index 0000000..dcd0a61
> --- /dev/null
> +++ b/drivers/memory/da8xx-ddrctl.c
> @@ -0,0 +1,77 @@
> +/*
> + * TI da8xx DDR2/mDDR controller driver
> + *
> + * Copyright (C) 2016 BayLibre SAS
> + *
> + * Author:
> + * Bartosz Golaszewski <bgolaszewski@baylibre.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define DA8XX_DDR_CTL_BASE 0xB0000000
This base addr should be the reg property of the node.
> +#define DA8XX_PBBPR_OFFSET 0x00000020
> +#define DA8XX_PBBPR_REG(p) ((p) + DA8XX_PBBPR_OFFSET)
Kevin
next prev parent reply other threads:[~2016-10-17 16:54 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-17 16:30 [PATCH 0/3] ARM: da850: new drivers for better LCDC support Bartosz Golaszewski
2016-10-17 16:30 ` Bartosz Golaszewski
2016-10-17 16:30 ` Bartosz Golaszewski
2016-10-17 16:30 ` [PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver Bartosz Golaszewski
2016-10-17 16:30 ` Bartosz Golaszewski
2016-10-17 16:30 ` Bartosz Golaszewski
2016-10-17 16:54 ` Kevin Hilman [this message]
2016-10-17 16:54 ` Kevin Hilman
2016-10-17 16:54 ` Kevin Hilman
2016-10-18 20:45 ` Laurent Pinchart
2016-10-18 20:45 ` Laurent Pinchart
2016-10-18 20:45 ` Laurent Pinchart
2016-10-17 16:30 ` [PATCH 2/3] ARM: bus: da8xx-syscfg: " Bartosz Golaszewski
2016-10-17 16:30 ` Bartosz Golaszewski
2016-10-17 16:30 ` Bartosz Golaszewski
2016-10-17 16:57 ` Kevin Hilman
2016-10-17 16:57 ` Kevin Hilman
2016-10-17 16:57 ` Kevin Hilman
2016-10-18 20:49 ` Laurent Pinchart
2016-10-18 20:49 ` Laurent Pinchart
2016-10-18 20:49 ` Laurent Pinchart
2016-10-19 8:26 ` Bartosz Golaszewski
2016-10-19 8:26 ` Bartosz Golaszewski
2016-10-19 8:26 ` Bartosz Golaszewski
2016-10-19 8:53 ` Laurent Pinchart
2016-10-19 8:53 ` Laurent Pinchart
2016-10-19 8:53 ` Laurent Pinchart
2016-10-20 16:57 ` Kevin Hilman
2016-10-20 16:57 ` Kevin Hilman
2016-10-20 16:57 ` Kevin Hilman
2016-10-20 18:05 ` Laurent Pinchart
2016-10-20 18:05 ` Laurent Pinchart
2016-10-20 19:39 ` Kevin Hilman
2016-10-20 19:39 ` Kevin Hilman
2016-10-20 19:39 ` Kevin Hilman
2016-10-21 9:25 ` Tomi Valkeinen
2016-10-21 9:25 ` Tomi Valkeinen
2016-10-21 9:25 ` Tomi Valkeinen
2016-10-21 9:53 ` Sekhar Nori
2016-10-21 9:53 ` Sekhar Nori
2016-10-21 9:56 ` Tomi Valkeinen
2016-10-21 9:56 ` Tomi Valkeinen
2016-10-21 9:56 ` Tomi Valkeinen
2016-10-17 16:30 ` [PATCH 3/3] ARM: dts: da850: add the syscfg and ddrctl nodes Bartosz Golaszewski
2016-10-17 16:30 ` Bartosz Golaszewski
2016-10-17 16:30 ` Bartosz Golaszewski
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