* [PATCH] ARM: dts: meson8: fix the size of the PMU registers
@ 2019-11-17 15:41 ` Martin Blumenstingl
0 siblings, 0 replies; 7+ messages in thread
From: Martin Blumenstingl @ 2019-11-17 15:41 UTC (permalink / raw)
To: linux-amlogic, khilman
Cc: Martin Blumenstingl, linux-kernel, linux-arm-kernel
The PMU registers are at least 0x18 bytes wide. Meson8b already uses a
size of 0x18. The structure of the PMU registers on Meson8 and Meson8b
is similar but not identical.
Meson8 and Meson8b have the following registers in common (starting at
AOBUS + 0xe0):
#define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2)
#define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2)
#define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2)
#define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2)
Meson8b additionally has these three registers:
#define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2)
#define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2)
#define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2)
Thus we can assume that the register size of the PMU IP blocks is
identical on both SoCs (and Meson8 just contains some reserved registers
in that area) because the CEC registers start right after the PMU
(AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2).
The upcoming power domain driver will need to read and write the
AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated
size is needed for that driver to work.
Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson8.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 5a7e3e5caebe..3c534cd50ee3 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -253,7 +253,7 @@
&aobus {
pmu: pmu@e0 {
compatible = "amlogic,meson8-pmu", "syscon";
- reg = <0xe0 0x8>;
+ reg = <0xe0 0x18>;
};
pinctrl_aobus: pinctrl@84 {
--
2.24.0
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH] ARM: dts: meson8: fix the size of the PMU registers
@ 2019-11-17 15:41 ` Martin Blumenstingl
0 siblings, 0 replies; 7+ messages in thread
From: Martin Blumenstingl @ 2019-11-17 15:41 UTC (permalink / raw)
To: linux-amlogic, khilman
Cc: Martin Blumenstingl, linux-kernel, linux-arm-kernel
The PMU registers are at least 0x18 bytes wide. Meson8b already uses a
size of 0x18. The structure of the PMU registers on Meson8 and Meson8b
is similar but not identical.
Meson8 and Meson8b have the following registers in common (starting at
AOBUS + 0xe0):
#define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2)
#define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2)
#define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2)
#define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2)
Meson8b additionally has these three registers:
#define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2)
#define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2)
#define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2)
Thus we can assume that the register size of the PMU IP blocks is
identical on both SoCs (and Meson8 just contains some reserved registers
in that area) because the CEC registers start right after the PMU
(AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2).
The upcoming power domain driver will need to read and write the
AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated
size is needed for that driver to work.
Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson8.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 5a7e3e5caebe..3c534cd50ee3 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -253,7 +253,7 @@
&aobus {
pmu: pmu@e0 {
compatible = "amlogic,meson8-pmu", "syscon";
- reg = <0xe0 0x8>;
+ reg = <0xe0 0x18>;
};
pinctrl_aobus: pinctrl@84 {
--
2.24.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH] ARM: dts: meson8: fix the size of the PMU registers
@ 2019-11-17 15:41 ` Martin Blumenstingl
0 siblings, 0 replies; 7+ messages in thread
From: Martin Blumenstingl @ 2019-11-17 15:41 UTC (permalink / raw)
To: linux-amlogic, khilman
Cc: linux-arm-kernel, linux-kernel, Martin Blumenstingl
The PMU registers are at least 0x18 bytes wide. Meson8b already uses a
size of 0x18. The structure of the PMU registers on Meson8 and Meson8b
is similar but not identical.
Meson8 and Meson8b have the following registers in common (starting at
AOBUS + 0xe0):
#define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2)
#define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2)
#define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2)
#define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2)
Meson8b additionally has these three registers:
#define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2)
#define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2)
#define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2)
Thus we can assume that the register size of the PMU IP blocks is
identical on both SoCs (and Meson8 just contains some reserved registers
in that area) because the CEC registers start right after the PMU
(AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2).
The upcoming power domain driver will need to read and write the
AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated
size is needed for that driver to work.
Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
arch/arm/boot/dts/meson8.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi
index 5a7e3e5caebe..3c534cd50ee3 100644
--- a/arch/arm/boot/dts/meson8.dtsi
+++ b/arch/arm/boot/dts/meson8.dtsi
@@ -253,7 +253,7 @@
&aobus {
pmu: pmu@e0 {
compatible = "amlogic,meson8-pmu", "syscon";
- reg = <0xe0 0x8>;
+ reg = <0xe0 0x18>;
};
pinctrl_aobus: pinctrl@84 {
--
2.24.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH] ARM: dts: meson8: fix the size of the PMU registers
2019-11-17 15:41 ` Martin Blumenstingl
(?)
@ 2019-11-21 23:46 ` Kevin Hilman
-1 siblings, 0 replies; 7+ messages in thread
From: Kevin Hilman @ 2019-11-21 23:46 UTC (permalink / raw)
To: Martin Blumenstingl, linux-amlogic
Cc: Martin Blumenstingl, linux-kernel, linux-arm-kernel
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> The PMU registers are at least 0x18 bytes wide. Meson8b already uses a
> size of 0x18. The structure of the PMU registers on Meson8 and Meson8b
> is similar but not identical.
>
> Meson8 and Meson8b have the following registers in common (starting at
> AOBUS + 0xe0):
> #define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2)
> #define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2)
> #define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2)
> #define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2)
>
> Meson8b additionally has these three registers:
> #define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2)
> #define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2)
> #define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2)
>
> Thus we can assume that the register size of the PMU IP blocks is
> identical on both SoCs (and Meson8 just contains some reserved registers
> in that area) because the CEC registers start right after the PMU
> (AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2).
>
> The upcoming power domain driver will need to read and write the
> AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated
> size is needed for that driver to work.
>
> Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Queued as a fix for v5.5-rc,
Kevin
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] ARM: dts: meson8: fix the size of the PMU registers
@ 2019-11-21 23:46 ` Kevin Hilman
0 siblings, 0 replies; 7+ messages in thread
From: Kevin Hilman @ 2019-11-21 23:46 UTC (permalink / raw)
To: Martin Blumenstingl, linux-amlogic
Cc: Martin Blumenstingl, linux-kernel, linux-arm-kernel
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> The PMU registers are at least 0x18 bytes wide. Meson8b already uses a
> size of 0x18. The structure of the PMU registers on Meson8 and Meson8b
> is similar but not identical.
>
> Meson8 and Meson8b have the following registers in common (starting at
> AOBUS + 0xe0):
> #define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2)
> #define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2)
> #define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2)
> #define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2)
>
> Meson8b additionally has these three registers:
> #define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2)
> #define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2)
> #define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2)
>
> Thus we can assume that the register size of the PMU IP blocks is
> identical on both SoCs (and Meson8 just contains some reserved registers
> in that area) because the CEC registers start right after the PMU
> (AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2).
>
> The upcoming power domain driver will need to read and write the
> AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated
> size is needed for that driver to work.
>
> Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Queued as a fix for v5.5-rc,
Kevin
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] ARM: dts: meson8: fix the size of the PMU registers
@ 2019-11-21 23:46 ` Kevin Hilman
0 siblings, 0 replies; 7+ messages in thread
From: Kevin Hilman @ 2019-11-21 23:46 UTC (permalink / raw)
To: Martin Blumenstingl, linux-amlogic
Cc: linux-arm-kernel, linux-kernel, Martin Blumenstingl
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> The PMU registers are at least 0x18 bytes wide. Meson8b already uses a
> size of 0x18. The structure of the PMU registers on Meson8 and Meson8b
> is similar but not identical.
>
> Meson8 and Meson8b have the following registers in common (starting at
> AOBUS + 0xe0):
> #define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2)
> #define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2)
> #define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2)
> #define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2)
>
> Meson8b additionally has these three registers:
> #define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2)
> #define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2)
> #define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2)
>
> Thus we can assume that the register size of the PMU IP blocks is
> identical on both SoCs (and Meson8 just contains some reserved registers
> in that area) because the CEC registers start right after the PMU
> (AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2).
>
> The upcoming power domain driver will need to read and write the
> AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated
> size is needed for that driver to work.
>
> Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores")
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Queued as a fix for v5.5-rc,
Kevin
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] ARM: dts: meson8: fix the size of the PMU registers
2019-11-17 15:41 ` Martin Blumenstingl
` (2 preceding siblings ...)
(?)
@ 2019-11-22 0:01 ` patchwork-bot+linux-amlogic
-1 siblings, 0 replies; 7+ messages in thread
From: patchwork-bot+linux-amlogic @ 2019-11-22 0:01 UTC (permalink / raw)
To: Martin Blumenstingl; +Cc: linux-amlogic, khilman
Hello:
This patch was applied to khilman/linux-amlogic.git (refs/heads/for-next).
On Sun, 17 Nov 2019 16:41:54 +0100 you wrote:
> The PMU registers are at least 0x18 bytes wide. Meson8b already uses a
> size of 0x18. The structure of the PMU registers on Meson8 and Meson8b
> is similar but not identical.
>
> Meson8 and Meson8b have the following registers in common (starting at
> AOBUS + 0xe0):
> #define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2)
> #define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2)
> #define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2)
> #define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2)
>
> [...]
Here is a summary with links:
- ARM: dts: meson8: fix the size of the PMU registers
https://git.kernel.org/khilman/linux-amlogic/c/edc0da604b716951a83c75464f793e0329a0f87a
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.wiki.kernel.org/userdoc/pwbot
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-11-22 0:01 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-11-17 15:41 [PATCH] ARM: dts: meson8: fix the size of the PMU registers Martin Blumenstingl
2019-11-17 15:41 ` Martin Blumenstingl
2019-11-17 15:41 ` Martin Blumenstingl
2019-11-21 23:46 ` Kevin Hilman
2019-11-21 23:46 ` Kevin Hilman
2019-11-21 23:46 ` Kevin Hilman
2019-11-22 0:01 ` patchwork-bot+linux-amlogic
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.