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From: khilman@baylibre.com (Kevin Hilman)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH v4 0/4] add clk controller driver for Meson-AXG SoC
Date: Wed, 06 Dec 2017 11:13:59 -0800	[thread overview]
Message-ID: <7hmv2vsm88.fsf@baylibre.com> (raw)
In-Reply-To: <20171201012452.27086-1-yixun.lan@amlogic.com> (Yixun Lan's message of "Fri, 1 Dec 2017 09:24:48 +0800")

Yixun Lan <yixun.lan@amlogic.com> writes:

> Add driver for the clk controller which found in Meson AXG SoC
>
>   Note, we deliberately create a seperate source file for the Meson AXG
> series, instead of sharing code with previous GXBB/GXL - the file axg.c
> It would help us maintaining the code more easily.

In addition to the DT node-name fixup (c.f. reply on v3 series), I think
this series should also include a patch that switches the UART over to
the new clock provider (it's currently using the xtal fixed clock.)

This will also provide a simple way to validate/test the series.

Kevin

WARNING: multiple messages have this Message-ID (diff)
From: Kevin Hilman <khilman@baylibre.com>
To: Yixun Lan <yixun.lan@amlogic.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>,
	 Jerome Brunet <jbrunet@baylibre.com>,
	 Rob Herring <robh+dt@kernel.org>,
	 Mark Rutland <mark.rutland@arm.com>,
	 Michael Turquette <mturquette@baylibre.com>,
	 Stephen Boyd <sboyd@codeaurora.org>,
	 Carlo Caione <carlo@caione.org>,
	 Qiufang Dai <qiufang.dai@amlogic.com>,
	 <linux-amlogic@lists.infradead.org>,
	 <devicetree@vger.kernel.org>,  <linux-clk@vger.kernel.org>,
	 <linux-arm-kernel@lists.infradead.org>,
	 <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 0/4] add clk controller driver for Meson-AXG SoC
Date: Wed, 06 Dec 2017 11:13:59 -0800	[thread overview]
Message-ID: <7hmv2vsm88.fsf@baylibre.com> (raw)
In-Reply-To: <20171201012452.27086-1-yixun.lan@amlogic.com> (Yixun Lan's message of "Fri, 1 Dec 2017 09:24:48 +0800")

Yixun Lan <yixun.lan@amlogic.com> writes:

> Add driver for the clk controller which found in Meson AXG SoC
>
>   Note, we deliberately create a seperate source file for the Meson AXG
> series, instead of sharing code with previous GXBB/GXL - the file axg.c
> It would help us maintaining the code more easily.

In addition to the DT node-name fixup (c.f. reply on v3 series), I think
this series should also include a patch that switches the UART over to
the new clock provider (it's currently using the xtal fixed clock.)

This will also provide a simple way to validate/test the series.

Kevin

WARNING: multiple messages have this Message-ID (diff)
From: khilman@baylibre.com (Kevin Hilman)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 0/4] add clk controller driver for Meson-AXG SoC
Date: Wed, 06 Dec 2017 11:13:59 -0800	[thread overview]
Message-ID: <7hmv2vsm88.fsf@baylibre.com> (raw)
In-Reply-To: <20171201012452.27086-1-yixun.lan@amlogic.com> (Yixun Lan's message of "Fri, 1 Dec 2017 09:24:48 +0800")

Yixun Lan <yixun.lan@amlogic.com> writes:

> Add driver for the clk controller which found in Meson AXG SoC
>
>   Note, we deliberately create a seperate source file for the Meson AXG
> series, instead of sharing code with previous GXBB/GXL - the file axg.c
> It would help us maintaining the code more easily.

In addition to the DT node-name fixup (c.f. reply on v3 series), I think
this series should also include a patch that switches the UART over to
the new clock provider (it's currently using the xtal fixed clock.)

This will also provide a simple way to validate/test the series.

Kevin

WARNING: multiple messages have this Message-ID (diff)
From: Kevin Hilman <khilman@baylibre.com>
To: Yixun Lan <yixun.lan@amlogic.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Rob Herring <robh+dt@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@codeaurora.org>,
	Carlo Caione <carlo@caione.org>,
	Qiufang Dai <qiufang.dai@amlogic.com>,
	linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 0/4] add clk controller driver for Meson-AXG SoC
Date: Wed, 06 Dec 2017 11:13:59 -0800	[thread overview]
Message-ID: <7hmv2vsm88.fsf@baylibre.com> (raw)
In-Reply-To: <20171201012452.27086-1-yixun.lan@amlogic.com> (Yixun Lan's message of "Fri, 1 Dec 2017 09:24:48 +0800")

Yixun Lan <yixun.lan@amlogic.com> writes:

> Add driver for the clk controller which found in Meson AXG SoC
>
>   Note, we deliberately create a seperate source file for the Meson AXG
> series, instead of sharing code with previous GXBB/GXL - the file axg.c
> It would help us maintaining the code more easily.

In addition to the DT node-name fixup (c.f. reply on v3 series), I think
this series should also include a patch that switches the UART over to
the new clock provider (it's currently using the xtal fixed clock.)

This will also provide a simple way to validate/test the series.

Kevin

  parent reply	other threads:[~2017-12-06 19:13 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-01  1:24 [PATCH v4 0/4] add clk controller driver for Meson-AXG SoC Yixun Lan
2017-12-01  1:24 ` Yixun Lan
2017-12-01  1:24 ` Yixun Lan
2017-12-01  1:24 ` Yixun Lan
2017-12-01  1:24 ` [PATCH v4 1/4] dt-bindings: clock: add compatible variant for the Meson-AXG Yixun Lan
2017-12-01  1:24   ` Yixun Lan
2017-12-01  1:24   ` Yixun Lan
2017-12-01  1:24   ` Yixun Lan
2017-12-01  1:24 ` [PATCH v4 2/4] clk: meson-axg: add clocks dt-bindings required header Yixun Lan
2017-12-01  1:24   ` Yixun Lan
2017-12-01  1:24   ` Yixun Lan
2017-12-01  1:24   ` Yixun Lan
2017-12-04 21:37   ` Rob Herring
2017-12-04 21:37     ` Rob Herring
2017-12-04 21:37     ` Rob Herring
2017-12-01  1:24 ` [PATCH v4 3/4] clk: meson-axg: add clock controller drivers Yixun Lan
2017-12-01  1:24   ` Yixun Lan
2017-12-01  1:24   ` Yixun Lan
2017-12-01  1:24   ` Yixun Lan
2017-12-07  8:40   ` Neil Armstrong
2017-12-07  8:40     ` Neil Armstrong
2017-12-07  8:40     ` Neil Armstrong
2017-12-01  1:24 ` [PATCH v4 4/4] arm64: dts: meson-axg: add clock DT info for Meson AXG SoC Yixun Lan
2017-12-01  1:24   ` Yixun Lan
2017-12-01  1:24   ` Yixun Lan
2017-12-01  1:24   ` Yixun Lan
2017-12-07  0:50   ` Kevin Hilman
2017-12-07  0:50     ` Kevin Hilman
2017-12-07  0:50     ` Kevin Hilman
2017-12-07  0:50     ` Kevin Hilman
2017-12-08 14:50     ` Yixun Lan
2017-12-08 14:50       ` Yixun Lan
2017-12-08 14:50       ` Yixun Lan
2017-12-08 14:50       ` Yixun Lan
2017-12-06 19:13 ` Kevin Hilman [this message]
2017-12-06 19:13   ` [PATCH v4 0/4] add clk controller driver for Meson-AXG SoC Kevin Hilman
2017-12-06 19:13   ` Kevin Hilman
2017-12-06 19:13   ` Kevin Hilman

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