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From: Kevin Hilman <khilman@baylibre.com>
To: Yu Tu <yu.tu@amlogic.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: "kelvin . zhang" <Kelvin.Zhang@amlogic.com>,
	"qi . duan" <qi.duan@amlogic.com>
Subject: Re: [PATCH V6 1/3] dt-bindings: clock: document Amlogic S4 SoC PLL & peripheral clock controller
Date: Tue, 24 Jan 2023 16:25:40 -0800	[thread overview]
Message-ID: <7ho7qnh33v.fsf@baylibre.com> (raw)
In-Reply-To: <9c34a8fc-de76-4beb-8841-9bcfd1a55cd1@amlogic.com>

Yu Tu <yu.tu@amlogic.com> writes:

> Hi Kevin,
>
> On 2023/1/19 8:38, Kevin Hilman wrote:
>> [ EXTERNAL EMAIL ]
>> 
>> Yu Tu <yu.tu@amlogic.com> writes:
>> 
>>> On 2023/1/16 16:29, Krzysztof Kozlowski wrote:
>> 
>> [...]
>> 
>>>>> diff --git a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
>>>>> new file mode 100644
>>>>> index 000000000000..bbec5094d5c3
>>>>> --- /dev/null
>>>>> +++ b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
>>>>> @@ -0,0 +1,131 @@
>>>>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>>>>
>>>> Unusual license... are you sure to license the bindings under GPLv4 or
>>>> GPLv5? Fine by me.
>>>>
>>>
>>> Yes.
>> 
>> The rest of the bindings for Amlogic SoCs are GPL-2.0 (without the '+').
>> Adding the dual-license for MIT seems fine, but adding the '+' is
>> curious.
>> 
>> It would be helpful if you could please explain why you'd like these
>> bindings to be licensed differently than the rest of the SoC family.
>> 
>
> I actually refer to the previous g12a Soc.
> https://elixir.bootlin.com/linux/v6.2-rc4/source/include/dt-bindings/clock/g12a-clkc.h
> https://elixir.bootlin.com/linux/v6.2-rc4/source/include/dt-bindings/clock/axg-clkc.h
> [...]
>
> So if you think it is not necessary, I will delete the '+' as you 
> suggested. Don't know what you choose?

Drop the `+`

Kevin

_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

WARNING: multiple messages have this Message-ID (diff)
From: Kevin Hilman <khilman@baylibre.com>
To: Yu Tu <yu.tu@amlogic.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: "kelvin . zhang" <Kelvin.Zhang@amlogic.com>,
	"qi . duan" <qi.duan@amlogic.com>
Subject: Re: [PATCH V6 1/3] dt-bindings: clock: document Amlogic S4 SoC PLL & peripheral clock controller
Date: Tue, 24 Jan 2023 16:25:40 -0800	[thread overview]
Message-ID: <7ho7qnh33v.fsf@baylibre.com> (raw)
In-Reply-To: <9c34a8fc-de76-4beb-8841-9bcfd1a55cd1@amlogic.com>

Yu Tu <yu.tu@amlogic.com> writes:

> Hi Kevin,
>
> On 2023/1/19 8:38, Kevin Hilman wrote:
>> [ EXTERNAL EMAIL ]
>> 
>> Yu Tu <yu.tu@amlogic.com> writes:
>> 
>>> On 2023/1/16 16:29, Krzysztof Kozlowski wrote:
>> 
>> [...]
>> 
>>>>> diff --git a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
>>>>> new file mode 100644
>>>>> index 000000000000..bbec5094d5c3
>>>>> --- /dev/null
>>>>> +++ b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
>>>>> @@ -0,0 +1,131 @@
>>>>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>>>>
>>>> Unusual license... are you sure to license the bindings under GPLv4 or
>>>> GPLv5? Fine by me.
>>>>
>>>
>>> Yes.
>> 
>> The rest of the bindings for Amlogic SoCs are GPL-2.0 (without the '+').
>> Adding the dual-license for MIT seems fine, but adding the '+' is
>> curious.
>> 
>> It would be helpful if you could please explain why you'd like these
>> bindings to be licensed differently than the rest of the SoC family.
>> 
>
> I actually refer to the previous g12a Soc.
> https://elixir.bootlin.com/linux/v6.2-rc4/source/include/dt-bindings/clock/g12a-clkc.h
> https://elixir.bootlin.com/linux/v6.2-rc4/source/include/dt-bindings/clock/axg-clkc.h
> [...]
>
> So if you think it is not necessary, I will delete the '+' as you 
> suggested. Don't know what you choose?

Drop the `+`

Kevin

WARNING: multiple messages have this Message-ID (diff)
From: Kevin Hilman <khilman@baylibre.com>
To: Yu Tu <yu.tu@amlogic.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Neil Armstrong <neil.armstrong@linaro.org>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: "kelvin . zhang" <Kelvin.Zhang@amlogic.com>,
	"qi . duan" <qi.duan@amlogic.com>
Subject: Re: [PATCH V6 1/3] dt-bindings: clock: document Amlogic S4 SoC PLL & peripheral clock controller
Date: Tue, 24 Jan 2023 16:25:40 -0800	[thread overview]
Message-ID: <7ho7qnh33v.fsf@baylibre.com> (raw)
In-Reply-To: <9c34a8fc-de76-4beb-8841-9bcfd1a55cd1@amlogic.com>

Yu Tu <yu.tu@amlogic.com> writes:

> Hi Kevin,
>
> On 2023/1/19 8:38, Kevin Hilman wrote:
>> [ EXTERNAL EMAIL ]
>> 
>> Yu Tu <yu.tu@amlogic.com> writes:
>> 
>>> On 2023/1/16 16:29, Krzysztof Kozlowski wrote:
>> 
>> [...]
>> 
>>>>> diff --git a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
>>>>> new file mode 100644
>>>>> index 000000000000..bbec5094d5c3
>>>>> --- /dev/null
>>>>> +++ b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
>>>>> @@ -0,0 +1,131 @@
>>>>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>>>>
>>>> Unusual license... are you sure to license the bindings under GPLv4 or
>>>> GPLv5? Fine by me.
>>>>
>>>
>>> Yes.
>> 
>> The rest of the bindings for Amlogic SoCs are GPL-2.0 (without the '+').
>> Adding the dual-license for MIT seems fine, but adding the '+' is
>> curious.
>> 
>> It would be helpful if you could please explain why you'd like these
>> bindings to be licensed differently than the rest of the SoC family.
>> 
>
> I actually refer to the previous g12a Soc.
> https://elixir.bootlin.com/linux/v6.2-rc4/source/include/dt-bindings/clock/g12a-clkc.h
> https://elixir.bootlin.com/linux/v6.2-rc4/source/include/dt-bindings/clock/axg-clkc.h
> [...]
>
> So if you think it is not necessary, I will delete the '+' as you 
> suggested. Don't know what you choose?

Drop the `+`

Kevin

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2023-01-25  0:26 UTC|newest]

Thread overview: 83+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-16  7:42 [PATCH V6 0/3] Add S4 SoC PLL and Peripheral clock controller Yu Tu
2023-01-16  7:42 ` Yu Tu
2023-01-16  7:42 ` Yu Tu
2023-01-16  7:42 ` [PATCH V6 1/3] dt-bindings: clock: document Amlogic S4 SoC PLL & peripheral " Yu Tu
2023-01-16  7:42   ` Yu Tu
2023-01-16  7:42   ` Yu Tu
2023-01-16  8:29   ` Krzysztof Kozlowski
2023-01-16  8:29     ` Krzysztof Kozlowski
2023-01-16  8:29     ` Krzysztof Kozlowski
2023-01-16  9:31     ` Yu Tu
2023-01-16  9:31       ` Yu Tu
2023-01-16  9:31       ` Yu Tu
2023-01-19  0:38       ` Kevin Hilman
2023-01-19  0:38         ` Kevin Hilman
2023-01-19  0:38         ` Kevin Hilman
2023-01-20  2:25         ` Yu Tu
2023-01-20  2:25           ` Yu Tu
2023-01-20  2:25           ` Yu Tu
2023-01-25  0:25           ` Kevin Hilman [this message]
2023-01-25  0:25             ` Kevin Hilman
2023-01-25  0:25             ` Kevin Hilman
2023-01-28  8:19             ` Yu Tu
2023-01-28  8:19               ` Yu Tu
2023-01-28  8:19               ` Yu Tu
2023-01-20  9:37       ` Jerome Brunet
2023-01-20  9:37         ` Jerome Brunet
2023-01-20  9:37         ` Jerome Brunet
2023-01-28  8:23         ` Yu Tu
2023-01-28  8:23           ` Yu Tu
2023-01-28  8:23           ` Yu Tu
2023-01-16  7:42 ` [PATCH V6 2/3] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver Yu Tu
2023-01-16  7:42   ` Yu Tu
2023-01-16  7:42   ` Yu Tu
2023-01-19 11:20   ` Jerome Brunet
2023-01-19 11:20     ` Jerome Brunet
2023-01-19 11:20     ` Jerome Brunet
2023-01-20  2:58     ` Yu Tu
2023-01-20  2:58       ` Yu Tu
2023-01-20  2:58       ` Yu Tu
2023-01-20  9:43       ` Jerome Brunet
2023-01-20  9:43         ` Jerome Brunet
2023-01-20  9:43         ` Jerome Brunet
2023-01-28  8:36         ` Yu Tu
2023-01-28  8:36           ` Yu Tu
2023-01-28  8:36           ` Yu Tu
2023-01-16  7:42 ` [PATCH V6 3/3] clk: meson: s4: add support for Amlogic S4 SoC peripheral clock controller Yu Tu
2023-01-16  7:42   ` Yu Tu
2023-01-19 11:37   ` Jerome Brunet
2023-01-19 11:37     ` Jerome Brunet
2023-01-19 11:37     ` Jerome Brunet
2023-01-20  3:33     ` Yu Tu
2023-01-20  3:33       ` Yu Tu
2023-01-20  3:33       ` Yu Tu
2023-01-20  9:47       ` Jerome Brunet
2023-01-20  9:47         ` Jerome Brunet
2023-01-20  9:47         ` Jerome Brunet
2023-01-28 10:17         ` Yu Tu
2023-01-28 10:17           ` Yu Tu
2023-01-28 10:17           ` Yu Tu
2023-01-30  9:06           ` Jerome Brunet
2023-01-30  9:06             ` Jerome Brunet
2023-01-30  9:06             ` Jerome Brunet
2023-01-30  9:41             ` Yu Tu
2023-01-30  9:41               ` Yu Tu
2023-01-30  9:41               ` Yu Tu
2023-01-30  9:47               ` Jerome Brunet
2023-01-30  9:47                 ` Jerome Brunet
2023-01-30  9:47                 ` Jerome Brunet
2023-01-30  9:59                 ` Yu Tu
2023-01-30  9:59                   ` Yu Tu
2023-01-30  9:59                   ` Yu Tu
2023-01-30 10:07                   ` Jerome Brunet
2023-01-30 10:07                     ` Jerome Brunet
2023-01-30 10:07                     ` Jerome Brunet
2023-01-31  3:29                     ` Yu Tu
2023-01-31  3:29                       ` Yu Tu
2023-01-31  3:29                       ` Yu Tu
2023-01-19 11:18 ` [PATCH V6 0/3] Add S4 SoC PLL and Peripheral " Jerome Brunet
2023-01-19 11:18   ` Jerome Brunet
2023-01-19 11:18   ` Jerome Brunet
2023-01-20  2:31   ` Yu Tu
2023-01-20  2:31     ` Yu Tu
2023-01-20  2:31     ` Yu Tu

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