Re: [PATCH 1/2] serial: 8250: Add RX trigger levels for U6_16550A

From: "Kryštof Černý" <cleverline1mc@gmail.com>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Jiri Slaby <jirislaby@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>,
	LKML <linux-kernel@vger.kernel.org>,
	linux-serial <linux-serial@vger.kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org,
	Miroslav Ondra <ondra@faster.cz>
Subject: Re: [PATCH 1/2] serial: 8250: Add RX trigger levels for U6_16550A
Date: Mon, 9 Nov 2026 16:37:43 +0100	[thread overview]
Message-ID: <800f8d42-e35d-47ec-bbe6-e437a86d6e70@gmail.com> (raw)
In-Reply-To: <469362ef-f0c5-45f2-746a-b4a3c51876a4@linux.intel.com>

> On Mon, 9 Nov 2026, Kryštof Černý via B4 Relay wrote:
> 
>> From: Kryštof Černý <cleverline1mc@gmail.com>
>>
>> PORT_U6_16550A has a 64-byte FIFO but no rxtrig_bytes table, so the
>> rx_trig_bytes sysfs attribute is not registered for ports of this type
>> and the RX trigger level cannot be read or changed from userspace.
>>
>> Add a table with 1, 16, 32 and 62 bytes, i.e. 1 character, FIFO 1/4
>> full, FIFO 1/2 full and FIFO 2 less than full. These are the levels the
>> Synopsys DesignWare UART uses for a 64-byte FIFO, and they match the
>> existing PORT_ALTR_16550_F64 table.
>>
>> The default FCR value of the type is unchanged, so the trigger level a
>> port starts with stays at 1/2 full. The only visible change for ports
>> already detected as U6_16550A by autoconfig is the new sysfs attribute.
>>
>> This prepares for 8250_dw selecting PORT_U6_16550A for DesignWare UARTs
>> with a 64-byte FIFO.
>>
>> Co-developed-by: Miroslav Ondra <ondra@faster.cz>
>> Signed-off-by: Miroslav Ondra <ondra@faster.cz>
>> Signed-off-by: Kryštof Černý <cleverline1mc@gmail.com>
>> ---
>>   drivers/tty/serial/8250/8250_port.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/tty/serial/8250/8250_port.c b/drivers/tty/serial/8250/8250_port.c
>> index 36b2b0a2c05c..a7acede62f40 100644
>> --- a/drivers/tty/serial/8250/8250_port.c
>> +++ b/drivers/tty/serial/8250/8250_port.c
>> @@ -163,6 +163,7 @@ static const struct serial8250_config uart_config[] = {
>>   		.fifo_size	= 64,
>>   		.tx_loadsz	= 64,
>>   		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
>> +		.rxtrig_bytes	= {1, 16, 32, 62},
> 
> Reusing U6 entry for DW UARTs seems misleading.
> 
> We've better mechanism coming up for defining rxtrig in a one pending
> series so this constant friction with the uart config types can be put
> into rest.
> 
> Please build on top of that other series and help in testing and reviewing
> it.

Thanks for the information, I started the work about a month ago
and not sure if the patch existed before. I will test the other series 
on my hardware. I like that approach more.