All of lore.kernel.org
 help / color / mirror / Atom feed
From: Heiko Stuebner <heiko@sntech.de>
To: atishp@atishpatra.org, Conor Dooley <mail@conchuod.ie>
Cc: ajones@ventanamicro.com, anup@brainfault.org,
	conor.dooley@microchip.com, jrtc27@jrtc27.com,
	linux-riscv@lists.infradead.org, lkp@intel.com,
	mchitale@ventanamicro.com, nathan@kernel.org,
	palmer@rivosinc.com, stable@vger.kernel.org,
	Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH v4] RISC-V: Clean up the Zicbom block size probing
Date: Tue, 13 Sep 2022 09:11:45 +0200	[thread overview]
Message-ID: <8114822.T7Z3S40VBb@phil> (raw)
In-Reply-To: <20220912224800.998121-1-mail@conchuod.ie>

Am Dienstag, 13. September 2022, 00:48:01 CEST schrieb Conor Dooley:
> From: Palmer Dabbelt <palmer@rivosinc.com>
> 
> This fixes two issues: I truncated the warning's hart ID when porting to
> the 64-bit hart ID code, and the original code's warning handling could
> fire on an uninitialized hart ID.
> 
> The biggest change here is that riscv_cbom_block_size is no longer
> initialized, as IMO the default isn't sane: there's nothing in the ISA
> that mandates any specific cache block size, so falling back to one will
> just silently produce the wrong answer on some systems.  This also
> changes the probing order so the cache block size is known before
> enabling Zicbom support.
> 
> CC: stable@vger.kernel.org
> CC: Andrew Jones <ajones@ventanamicro.com>
> CC: Heiko Stuebner <heiko@sntech.de>
> CC: Atish Patra <atishp@rivosinc.com>
> Fixes: 3aefb2ee5bdd ("riscv: implement Zicbom-based CMO instructions + the t-head variant")
> Fixes: 1631ba1259d6 ("riscv: Add support for non-coherent devices using zicbom extension")
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> [Conor: fixed the redefinition errors]
> Tested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>




_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko@sntech.de>
To: atishp@atishpatra.org, Conor Dooley <mail@conchuod.ie>
Cc: ajones@ventanamicro.com, anup@brainfault.org,
	conor.dooley@microchip.com, jrtc27@jrtc27.com,
	linux-riscv@lists.infradead.org, lkp@intel.com,
	mchitale@ventanamicro.com, nathan@kernel.org,
	palmer@rivosinc.com, stable@vger.kernel.org,
	Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH v4] RISC-V: Clean up the Zicbom block size probing
Date: Tue, 13 Sep 2022 09:11:45 +0200	[thread overview]
Message-ID: <8114822.T7Z3S40VBb@phil> (raw)
In-Reply-To: <20220912224800.998121-1-mail@conchuod.ie>

Am Dienstag, 13. September 2022, 00:48:01 CEST schrieb Conor Dooley:
> From: Palmer Dabbelt <palmer@rivosinc.com>
> 
> This fixes two issues: I truncated the warning's hart ID when porting to
> the 64-bit hart ID code, and the original code's warning handling could
> fire on an uninitialized hart ID.
> 
> The biggest change here is that riscv_cbom_block_size is no longer
> initialized, as IMO the default isn't sane: there's nothing in the ISA
> that mandates any specific cache block size, so falling back to one will
> just silently produce the wrong answer on some systems.  This also
> changes the probing order so the cache block size is known before
> enabling Zicbom support.
> 
> CC: stable@vger.kernel.org
> CC: Andrew Jones <ajones@ventanamicro.com>
> CC: Heiko Stuebner <heiko@sntech.de>
> CC: Atish Patra <atishp@rivosinc.com>
> Fixes: 3aefb2ee5bdd ("riscv: implement Zicbom-based CMO instructions + the t-head variant")
> Fixes: 1631ba1259d6 ("riscv: Add support for non-coherent devices using zicbom extension")
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> [Conor: fixed the redefinition errors]
> Tested-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Reviewed-by: Heiko Stuebner <heiko@sntech.de>




  reply	other threads:[~2022-09-13  7:12 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-12 22:48 [PATCH v4] RISC-V: Clean up the Zicbom block size probing Conor Dooley
2022-09-12 22:48 ` Conor Dooley
2022-09-13  7:11 ` Heiko Stuebner [this message]
2022-09-13  7:11   ` Heiko Stuebner
2022-09-13  9:40 ` Nathan Chancellor
2022-09-13  9:40   ` Nathan Chancellor
2022-09-13 11:17   ` Palmer Dabbelt
2022-09-13 11:17     ` Palmer Dabbelt

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=8114822.T7Z3S40VBb@phil \
    --to=heiko@sntech.de \
    --cc=ajones@ventanamicro.com \
    --cc=anup@brainfault.org \
    --cc=atishp@atishpatra.org \
    --cc=atishp@rivosinc.com \
    --cc=conor.dooley@microchip.com \
    --cc=jrtc27@jrtc27.com \
    --cc=linux-riscv@lists.infradead.org \
    --cc=lkp@intel.com \
    --cc=mail@conchuod.ie \
    --cc=mchitale@ventanamicro.com \
    --cc=nathan@kernel.org \
    --cc=palmer@rivosinc.com \
    --cc=stable@vger.kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.