Re: [PATCH v7 03/13] PCI: cadence: Add register definitions for HPA(High Perf Architecture)

[Krzysztof Kozlowski <krzk@kernel.org>]

On 13/08/2025 06:23, hans.zhang@cixtech.com wrote:
>  static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size)
>  {
>  	void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);
> @@ -313,19 +410,17 @@ static inline void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep)
>  #endif
>  
>  void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
> -
>  void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
>  				   u32 r, bool is_io,
>  				   u64 cpu_addr, u64 pci_addr, size_t size);
> -
>  void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
>  						  u8 busnr, u8 fn,
>  						  u32 r, u64 cpu_addr);
> -
>  void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
>  void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
> -int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
> -int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
> +int  cdns_pcie_enable_phy(struct cdns_pcie *pcie);
> +int  cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);

I don't understand how this (and many other pieces here) is related to
"add register definitions".

This is not a register definition.



Best regards,
Krzysztof