From: "Jernej Škrabec" <jernej.skrabec@gmail.com>
To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org,
Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Samuel Holland <samuel@sholland.org>,
Maxime Ripard <mripard@kernel.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Subject: Re: [PATCH v7 5/7] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
Date: Wed, 13 Dec 2023 21:11:52 +0100 [thread overview]
Message-ID: <8310859.T7Z3S40VBb@archlinux> (raw)
In-Reply-To: <20231122141426.329694-6-paul.kocialkowski@bootlin.com>
On Wednesday, November 22, 2023 3:14:23 PM CET Paul Kocialkowski wrote:
> MIPI CSI-2 is supported on the A83T with a dedicated controller that
> covers both the protocol and D-PHY. It is connected to the only CSI
> receiver with a fwnode graph link. Note that the CSI receiver supports
> both this MIPI CSI-2 source and a parallel source.
>
> An empty port with a label for the MIPI CSI-2 sensor input is also
> defined for convenience.
>
> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
> ---
> arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 43 +++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
> index 94eb3bfc989e..b74c3f9e6598 100644
> --- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
> @@ -1062,6 +1062,49 @@ csi: camera@1cb0000 {
> clock-names = "bus", "mod", "ram";
> resets = <&ccu RST_BUS_CSI>;
> status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> +
> + csi_in_mipi_csi2: endpoint {
> + remote-endpoint = <&mipi_csi2_out_csi>;
> + };
> + };
> + };
> + };
> +
> + mipi_csi2: csi@1cb1000 {
> + compatible = "allwinner,sun8i-a83t-mipi-csi2";
> + reg = <0x01cb1000 0x1000>;
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI_SCLK>,
> + <&ccu CLK_MIPI_CSI>,
> + <&ccu CLK_CSI_MISC>;
> + clock-names = "bus", "mod", "mipi", "misc";
> + resets = <&ccu RST_BUS_CSI>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mipi_csi2_in: port@0 {
> + reg = <0>;
> + };
> +
> + mipi_csi2_out: port@1 {
> + reg = <1>;
> +
> + mipi_csi2_out_csi: endpoint {
> + remote-endpoint = <&csi_in_mipi_csi2>;
> + };
> + };
> + };
> };
>
> hdmi: hdmi@1ee0000 {
>
WARNING: multiple messages have this Message-ID (diff)
From: "Jernej Škrabec" <jernej.skrabec@gmail.com>
To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org,
Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
Samuel Holland <samuel@sholland.org>,
Maxime Ripard <mripard@kernel.org>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Subject: Re: [PATCH v7 5/7] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
Date: Wed, 13 Dec 2023 21:11:52 +0100 [thread overview]
Message-ID: <8310859.T7Z3S40VBb@archlinux> (raw)
In-Reply-To: <20231122141426.329694-6-paul.kocialkowski@bootlin.com>
On Wednesday, November 22, 2023 3:14:23 PM CET Paul Kocialkowski wrote:
> MIPI CSI-2 is supported on the A83T with a dedicated controller that
> covers both the protocol and D-PHY. It is connected to the only CSI
> receiver with a fwnode graph link. Note that the CSI receiver supports
> both this MIPI CSI-2 source and a parallel source.
>
> An empty port with a label for the MIPI CSI-2 sensor input is also
> defined for convenience.
>
> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
> ---
> arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 43 +++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
> index 94eb3bfc989e..b74c3f9e6598 100644
> --- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
> +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
> @@ -1062,6 +1062,49 @@ csi: camera@1cb0000 {
> clock-names = "bus", "mod", "ram";
> resets = <&ccu RST_BUS_CSI>;
> status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> +
> + csi_in_mipi_csi2: endpoint {
> + remote-endpoint = <&mipi_csi2_out_csi>;
> + };
> + };
> + };
> + };
> +
> + mipi_csi2: csi@1cb1000 {
> + compatible = "allwinner,sun8i-a83t-mipi-csi2";
> + reg = <0x01cb1000 0x1000>;
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI_SCLK>,
> + <&ccu CLK_MIPI_CSI>,
> + <&ccu CLK_CSI_MISC>;
> + clock-names = "bus", "mod", "mipi", "misc";
> + resets = <&ccu RST_BUS_CSI>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mipi_csi2_in: port@0 {
> + reg = <0>;
> + };
> +
> + mipi_csi2_out: port@1 {
> + reg = <1>;
> +
> + mipi_csi2_out_csi: endpoint {
> + remote-endpoint = <&csi_in_mipi_csi2>;
> + };
> + };
> + };
> };
>
> hdmi: hdmi@1ee0000 {
>
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next prev parent reply other threads:[~2023-12-13 20:11 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-22 14:14 [PATCH v7 0/7] Allwinner A31/A83T MIPI CSI-2 and A31 ISP / Platform Support Paul Kocialkowski
2023-11-22 14:14 ` Paul Kocialkowski
2023-11-22 14:14 ` [PATCH v7 1/7] clk: sunxi-ng: v3s: Export MBUS and DRAM clocks to the public header Paul Kocialkowski
2023-11-22 14:14 ` Paul Kocialkowski
2023-11-22 14:14 ` [PATCH v7 2/7] ARM: dts: sun8i: v3s: Add mbus node to represent the interconnect Paul Kocialkowski
2023-11-22 14:14 ` Paul Kocialkowski
2023-11-22 14:14 ` [PATCH v7 3/7] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support Paul Kocialkowski
2023-11-22 14:14 ` Paul Kocialkowski
2023-12-13 20:07 ` Jernej Škrabec
2023-12-13 20:07 ` Jernej Škrabec
2023-11-22 14:14 ` [PATCH v7 4/7] ARM: dts: sun8i: v3s: Add support for the ISP Paul Kocialkowski
2023-11-22 14:14 ` Paul Kocialkowski
2023-12-13 20:09 ` Jernej Škrabec
2023-12-13 20:09 ` Jernej Škrabec
2023-11-22 14:14 ` [PATCH v7 5/7] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node Paul Kocialkowski
2023-11-22 14:14 ` Paul Kocialkowski
2023-12-13 20:11 ` Jernej Škrabec [this message]
2023-12-13 20:11 ` Jernej Škrabec
2023-11-22 14:14 ` [PATCH v7 6/7] ARM: dts: sun8i-a83t: Add BananaPi M3 OV5640 camera overlay Paul Kocialkowski
2023-11-22 14:14 ` Paul Kocialkowski
2023-12-13 20:25 ` Jernej Škrabec
2023-12-13 20:25 ` Jernej Škrabec
2023-11-22 14:14 ` [PATCH v7 7/7] ARM: dts: sun8i-a83t: Add BananaPi M3 OV8865 " Paul Kocialkowski
2023-11-22 14:14 ` Paul Kocialkowski
2023-12-13 20:26 ` Jernej Škrabec
2023-12-13 20:26 ` Jernej Škrabec
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