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From: Nikunj A Dadhania <nikunj@amd.com>
To: Tom Lendacky <thomas.lendacky@amd.com>, <seanjc@google.com>,
	<pbonzini@redhat.com>, <kvm@vger.kernel.org>
Cc: <santosh.shukla@amd.com>, <bp@alien8.de>, <isaku.yamahata@intel.com>
Subject: Re: [PATCH v3 4/5] KVM: SVM: Prevent writes to TSC MSR when Secure TSC is enabled
Date: Tue, 18 Feb 2025 09:20:12 +0000	[thread overview]
Message-ID: <85bjuzip83.fsf@amd.com> (raw)
In-Reply-To: <cd36710b-957e-bfe9-7904-e1041f00d98a@amd.com>

Tom Lendacky <thomas.lendacky@amd.com> writes:

> On 2/17/25 04:22, Nikunj A Dadhania wrote:

>> @@ -3161,6 +3161,20 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
>>  
>>  		svm->tsc_aux = data;
>>  		break;
>> +	case MSR_IA32_TSC:
>> +		/*
>> +		 * If Secure TSC is enabled, do not emulate TSC write as TSC calculation
>> +		 * ignores the TSC_OFFSET and TSC_SCALE control fields, record the error
>> +		 * and return a #GP. Allow the TSC to be initialized until the guest state
>> +		 * is protected to prevent unexpected VMM errors.
>> +		 */
>> +		if (vcpu->arch.guest_state_protected && snp_secure_tsc_enabled(vcpu->kvm)) {
>
> I'm not sure if it matters, but do we need to differentiate between
> guest and host write in this situation at all in regards to the message
> or return code?
>

Yes, I think we can have something like the below:

+	case MSR_IA32_TSC:
+		/*
+		 * For Secure TSC enabled VM, do not emulate TSC write as the
+		 * TSC calculation ignores the TSC_OFFSET and TSC_SCALE control
+		 * fields.
+		 *
+		 * Guest writes: Record the error and return a #GP.
+		 * Host writes are ignored.
+		 */
+		if (snp_secure_tsc_enabled(vcpu->kvm)) {
+			if (!msr->host_initiated) {
+				vcpu_unimpl(vcpu, "unimplemented IA32_TSC for Secure TSC\n");
+				return 1;
+			} else
+				return 0;
+		}
+
+		ret = kvm_set_msr_common(vcpu, msr);
+		break;

>> +			vcpu_unimpl(vcpu, "unimplemented IA32_TSC for secure tsc\n");
>
> s/secure tsc/Secure TSC/ ?
>

Ack,

Thanks
Nikunj

  reply	other threads:[~2025-02-18  9:20 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-17 10:22 [PATCH v3 0/5] Enable Secure TSC for SEV-SNP Nikunj A Dadhania
2025-02-17 10:22 ` [PATCH v3 1/5] x86/cpufeatures: Add SNP Secure TSC Nikunj A Dadhania
2025-02-17 10:22 ` [PATCH v3 2/5] crypto: ccp: Add missing member in SNP_LAUNCH_START command structure Nikunj A Dadhania
2025-02-17 19:18   ` Tom Lendacky
2025-02-18  7:57     ` Nikunj A Dadhania
2025-02-17 10:22 ` [PATCH v3 3/5] KVM: SVM: Add GUEST_TSC_FREQ MSR for Secure TSC enabled guests Nikunj A Dadhania
2025-02-17 18:28   ` Tom Lendacky
2025-02-18  8:07     ` Nikunj A Dadhania
2025-02-17 10:22 ` [PATCH v3 4/5] KVM: SVM: Prevent writes to TSC MSR when Secure TSC is enabled Nikunj A Dadhania
2025-02-17 18:58   ` Tom Lendacky
2025-02-18  9:20     ` Nikunj A Dadhania [this message]
2025-02-17 10:22 ` [PATCH v3 5/5] KVM: SVM: Enable Secure TSC for SNP guests Nikunj A Dadhania
2025-02-17 18:34   ` Tom Lendacky
2025-02-18  8:10     ` Nikunj A Dadhania

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