From: Nikunj A Dadhania <nikunj@amd.com>
To: Tom Lendacky <thomas.lendacky@amd.com>, <seanjc@google.com>,
<pbonzini@redhat.com>, <kvm@vger.kernel.org>
Cc: <santosh.shukla@amd.com>, <bp@alien8.de>, <isaku.yamahata@intel.com>
Subject: Re: [PATCH v3 5/5] KVM: SVM: Enable Secure TSC for SNP guests
Date: Tue, 18 Feb 2025 08:10:06 +0000 [thread overview]
Message-ID: <85eczvisgx.fsf@amd.com> (raw)
In-Reply-To: <fcd943d2-9c6e-1662-6b6e-37e5235fe57f@amd.com>
Tom Lendacky <thomas.lendacky@amd.com> writes:
> On 2/17/25 04:22, Nikunj A Dadhania wrote:
>> From: Ketan Chaturvedi <Ketan.Chaturvedi@amd.com>
>> if (rc) {
>> @@ -2929,6 +2943,9 @@ void __init sev_set_cpu_caps(void)
>> if (sev_snp_enabled) {
>> kvm_cpu_cap_set(X86_FEATURE_SEV_SNP);
>> kvm_caps.supported_vm_types |= BIT(KVM_X86_SNP_VM);
>> +
>> + if (cpu_feature_enabled(X86_FEATURE_SNP_SECURE_TSC))
>> + kvm_cpu_cap_set(X86_FEATURE_SNP_SECURE_TSC);
>
> kvm_cpu_cap_check_and_set()
Sure, I have updated the patch.
Regards
Nikunj
prev parent reply other threads:[~2025-02-18 8:10 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-17 10:22 [PATCH v3 0/5] Enable Secure TSC for SEV-SNP Nikunj A Dadhania
2025-02-17 10:22 ` [PATCH v3 1/5] x86/cpufeatures: Add SNP Secure TSC Nikunj A Dadhania
2025-02-17 10:22 ` [PATCH v3 2/5] crypto: ccp: Add missing member in SNP_LAUNCH_START command structure Nikunj A Dadhania
2025-02-17 19:18 ` Tom Lendacky
2025-02-18 7:57 ` Nikunj A Dadhania
2025-02-17 10:22 ` [PATCH v3 3/5] KVM: SVM: Add GUEST_TSC_FREQ MSR for Secure TSC enabled guests Nikunj A Dadhania
2025-02-17 18:28 ` Tom Lendacky
2025-02-18 8:07 ` Nikunj A Dadhania
2025-02-17 10:22 ` [PATCH v3 4/5] KVM: SVM: Prevent writes to TSC MSR when Secure TSC is enabled Nikunj A Dadhania
2025-02-17 18:58 ` Tom Lendacky
2025-02-18 9:20 ` Nikunj A Dadhania
2025-02-17 10:22 ` [PATCH v3 5/5] KVM: SVM: Enable Secure TSC for SNP guests Nikunj A Dadhania
2025-02-17 18:34 ` Tom Lendacky
2025-02-18 8:10 ` Nikunj A Dadhania [this message]
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