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From: Marc Zyngier <maz@kernel.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Hector Martin <marcan@marcan.st>, Sven Peter <sven@svenpeter.dev>,
	Alyssa Rosenzweig <alyssa@rosenzweig.io>,
	Atish Patra <atishp@atishpatra.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	asahi@lists.linux.dev
Subject: Re: [PATCH v16 0/9] RISC-V IPI Improvements
Date: Sun, 05 Feb 2023 11:04:14 +0000	[thread overview]
Message-ID: <86357k1ihd.wl-maz@kernel.org> (raw)
In-Reply-To: <20230103141221.772261-1-apatel@ventanamicro.com>

On Tue, 03 Jan 2023 14:12:12 +0000,
Anup Patel <apatel@ventanamicro.com> wrote:
> 
> This series aims to improve IPI support in Linux RISC-V in following ways:
>  1) Treat IPIs as normal per-CPU interrupts instead of having custom RISC-V
>     specific hooks. This also makes Linux RISC-V IPI support aligned with
>     other architectures.
>  2) Remote TLB flushes and icache flushes should prefer local IPIs instead
>     of SBI calls whenever we have specialized hardware (such as RISC-V AIA
>     IMSIC and RISC-V SWI) which allows S-mode software to directly inject
>     IPIs without any assistance from M-mode runtime firmware.

[...]

I'm queuing patches 3 and 9 via the irqchip tree as they are
standalone.

For the rest, I need an Ack from the riscv maintainers as they change
a large amount of arch-specific code, and the couple of irqchip
patches depend on these changes.

Palmer, Paul?

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Anup Patel <apatel@ventanamicro.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	Hector Martin <marcan@marcan.st>, Sven Peter <sven@svenpeter.dev>,
	Alyssa Rosenzweig <alyssa@rosenzweig.io>,
	Atish Patra <atishp@atishpatra.org>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	asahi@lists.linux.dev
Subject: Re: [PATCH v16 0/9] RISC-V IPI Improvements
Date: Sun, 05 Feb 2023 11:04:14 +0000	[thread overview]
Message-ID: <86357k1ihd.wl-maz@kernel.org> (raw)
In-Reply-To: <20230103141221.772261-1-apatel@ventanamicro.com>

On Tue, 03 Jan 2023 14:12:12 +0000,
Anup Patel <apatel@ventanamicro.com> wrote:
> 
> This series aims to improve IPI support in Linux RISC-V in following ways:
>  1) Treat IPIs as normal per-CPU interrupts instead of having custom RISC-V
>     specific hooks. This also makes Linux RISC-V IPI support aligned with
>     other architectures.
>  2) Remote TLB flushes and icache flushes should prefer local IPIs instead
>     of SBI calls whenever we have specialized hardware (such as RISC-V AIA
>     IMSIC and RISC-V SWI) which allows S-mode software to directly inject
>     IPIs without any assistance from M-mode runtime firmware.

[...]

I'm queuing patches 3 and 9 via the irqchip tree as they are
standalone.

For the rest, I need an Ack from the riscv maintainers as they change
a large amount of arch-specific code, and the couple of irqchip
patches depend on these changes.

Palmer, Paul?

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  parent reply	other threads:[~2023-02-05 11:04 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-03 14:12 [PATCH v16 0/9] RISC-V IPI Improvements Anup Patel
2023-01-03 14:12 ` Anup Patel
2023-01-03 14:12 ` [PATCH v16 1/9] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel
2023-01-03 14:12   ` Anup Patel
2023-01-03 14:12 ` [PATCH v16 2/9] irqchip/riscv-intc: Allow drivers to directly discover INTC hwnode Anup Patel
2023-01-03 14:12   ` Anup Patel
2023-01-03 14:12 ` [PATCH v16 3/9] genirq: Add mechanism to multiplex a single HW IPI Anup Patel
2023-01-03 14:12   ` Anup Patel
2023-02-05 11:29   ` [irqchip: irq/irqchip-next] " irqchip-bot for Anup Patel
2023-01-03 14:12 ` [PATCH v16 4/9] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel
2023-01-03 14:12   ` Anup Patel
2023-01-03 14:12 ` [PATCH v16 5/9] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel
2023-01-03 14:12   ` Anup Patel
2023-01-03 14:12 ` [PATCH v16 6/9] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel
2023-01-03 14:12   ` Anup Patel
2023-01-03 14:12 ` [PATCH v16 7/9] RISC-V: Use IPIs for remote icache " Anup Patel
2023-01-03 14:12   ` Anup Patel
2023-01-03 14:12 ` [PATCH v16 8/9] irqchip/riscv-intc: Add empty irq_eoi() for chained irq handlers Anup Patel
2023-01-03 14:12   ` Anup Patel
2023-01-03 14:12 ` [PATCH v16 9/9] irqchip/apple-aic: Move over to core ipi-mux Anup Patel
2023-01-03 14:12   ` Anup Patel
2023-02-05 11:29   ` [irqchip: irq/irqchip-next] " irqchip-bot for Marc Zyngier
2023-01-12 12:17 ` [PATCH v16 0/9] RISC-V IPI Improvements Anup Patel
2023-01-12 12:17   ` Anup Patel
2023-01-20  3:29   ` Anup Patel
2023-01-20  3:29     ` Anup Patel
2023-02-05 11:04 ` Marc Zyngier [this message]
2023-02-05 11:04   ` Marc Zyngier
2023-02-15  3:17   ` Palmer Dabbelt
2023-02-15  3:17     ` Palmer Dabbelt
2023-02-20  8:35     ` Marc Zyngier
2023-02-20  8:35       ` Marc Zyngier
2023-02-20  9:50       ` Anup Patel
2023-02-20  9:50         ` Anup Patel

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