From: Marc Zyngier <maz@kernel.org>
To: Mark Kettenis <mark.kettenis@xs4all.nl>
Cc: linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
asahi@lists.linux.dev, alyssa@rosenzweig.io, j@jannau.net,
marcan@marcan.st, sven@svenpeter.dev, bhelgaas@google.com,
lpieralisi@kernel.org, kw@linux.com,
manivannan.sadhasivam@linaro.org, robh@kernel.org,
krzk+dt@kernel.org
Subject: Re: [PATCH v2 01/13] dt-bindings: pci: apple,pcie: Add t6020 compatible string
Date: Tue, 25 Mar 2025 11:02:30 +0000 [thread overview]
Message-ID: <864izhmkzd.wl-maz@kernel.org> (raw)
In-Reply-To: <87iknx75at.fsf@bloch.sibelius.xs4all.nl>
Hi Mark,
On Tue, 25 Mar 2025 10:50:18 +0000,
Mark Kettenis <mark.kettenis@xs4all.nl> wrote:
>
> > From: Marc Zyngier <maz@kernel.org>
> > Date: Tue, 25 Mar 2025 10:25:58 +0000
>
> Hi Marc,
>
> Sorry for not spotting this in the earlier versions, but:
No worries -- I expected issues in that department.
>
> > From: Alyssa Rosenzweig <alyssa@rosenzweig.io>
> >
> > t6020 adds some register ranges compared to t8103, so requires
> > a new compatible as well as the new PHY registers themselves.
> >
> > Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
> > [maz: added PHY registers]
> > Signed-off-by: Marc Zyngier <maz@kernel.org>
> > ---
> > Documentation/devicetree/bindings/pci/apple,pcie.yaml | 11 ++++++++++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml
> > index c8775f9cb0713..77554899b9420 100644
> > --- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml
> > @@ -17,6 +17,10 @@ description: |
> > implements its root ports. But the ATU found on most DesignWare
> > PCIe host bridges is absent.
> >
> > + On systems derived from T602x, the PHY registers are in a region
> > + separate from the port registers. In that case, there is one PHY
> > + register range per port register range.
> > +
> > All root ports share a single ECAM space, but separate GPIOs are
> > used to take the PCI devices on those ports out of reset. Therefore
> > the standard "reset-gpios" and "max-link-speed" properties appear on
> > @@ -35,11 +39,12 @@ properties:
> > - apple,t8103-pcie
> > - apple,t8112-pcie
> > - apple,t6000-pcie
> > + - apple,t6020-pcie
> > - const: apple,pcie
>
> Since the T602x PCIe controller has a different register layout, it
> isn't compatible with the others, so it should not include the
> "apple,pcie" compatible. The "downstream" device trees for
> T602x-based devices do indeed not list "apple,pcie" as a compatible.
> So I think this needs to be written as:
>
> compatible:
> oneOf:
> - items:
> - enum:
> - apple,t8103-pcie
> - apple,t8112-pcie
> - apple,t6000-pcie
> - const: apple,pcie
> - const: apple,t6020-pcie
Ah, indeed, that's a good point. Thanks for that.
Whilst I have your attention, how about my question below:
>
> >
> > reg:
> > minItems: 3
> > - maxItems: 6
> > + maxItems: 10
> >
> > reg-names:
> > minItems: 3
> > @@ -50,6 +55,10 @@ properties:
> > - const: port1
> > - const: port2
> > - const: port3
> > + - const: phy0
> > + - const: phy1
> > + - const: phy2
> > + - const: phy3
Do we need to make this t6020 specific?
Obviously, separate PHY registers do not make much sense before t6020,
but I couldn't find a way to describe that. I don't even know if
that's a desirable outcome.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2025-03-25 11:02 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-25 10:25 [PATCH v2 00/13] PCI: apple: Add support for t6020 Marc Zyngier
2025-03-25 10:25 ` [PATCH v2 01/13] dt-bindings: pci: apple,pcie: Add t6020 compatible string Marc Zyngier
2025-03-25 10:50 ` Mark Kettenis
2025-03-25 11:02 ` Marc Zyngier [this message]
2025-03-25 15:41 ` Mark Kettenis
2025-03-25 16:48 ` Marc Zyngier
2025-03-26 19:51 ` Rob Herring
2025-03-25 10:25 ` [PATCH v2 02/13] PCI: host-generic: Extract an ecam bridge creation helper from pci_host_common_probe() Marc Zyngier
2025-03-25 10:26 ` [PATCH v2 03/13] PCI: ecam: Allow cfg->priv to be pre-populated from the root port device Marc Zyngier
2025-03-25 10:26 ` [PATCH v2 04/13] PCI: apple: Move over to standalone probing Marc Zyngier
2025-03-25 10:26 ` [PATCH v2 05/13] PCI: apple: Dynamically allocate RID-to_SID bitmap Marc Zyngier
2025-03-25 10:26 ` [PATCH v2 06/13] PCI: apple: Move away from INTMSK{SET,CLR} for INTx and private interrupts Marc Zyngier
2025-03-25 10:26 ` [PATCH v2 07/13] PCI: apple: Fix missing OF node reference in apple_pcie_setup_port Marc Zyngier
2025-03-25 10:26 ` [PATCH v2 08/13] PCI: apple: Set only available ports up Marc Zyngier
2025-03-25 13:25 ` Rob Herring
2025-03-25 10:26 ` [PATCH v2 09/13] PCI: apple: Move port PHY registers to their own reg items Marc Zyngier
2025-03-25 10:26 ` [PATCH v2 10/13] PCI: apple: Drop poll for CORE_RC_PHYIF_STAT_REFCLK Marc Zyngier
2025-03-25 10:26 ` [PATCH v2 11/13] PCI: apple: Use gpiod_set_value_cansleep in probe flow Marc Zyngier
2025-03-25 10:26 ` [PATCH v2 12/13] PCI: apple: Abstract register offsets via a SoC-specific structure Marc Zyngier
2025-03-25 10:26 ` [PATCH v2 13/13] PCI: apple: Add T602x PCIe support Marc Zyngier
2025-03-25 13:31 ` [PATCH v2 00/13] PCI: apple: Add support for t6020 Rob Herring
2025-03-25 14:50 ` Alyssa Rosenzweig
2025-03-31 11:28 ` Janne Grunau
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