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From: Marc Zyngier <marc.zyngier@arm.com>
To: Paul Burton <paul.burton@mips.com>
Cc: Jason Cooper <jason@lakedaemon.net>,
	Thomas Gleixner <tglx@linutronix.de>, <linux-mips@linux-mips.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/8] irqchip: mips-gic: Use irq_cpu_online to (un)mask all-VP(E) IRQs
Date: Tue, 31 Oct 2017 01:35:02 +0000	[thread overview]
Message-ID: <867evc5cc9.fsf@arm.com> (raw)
In-Reply-To: <20171030163616.tsti7thormxlnxuo@pburton-laptop> (Paul Burton's message of "Mon, 30 Oct 2017 09:36:16 -0700")

On Mon, Oct 30 2017 at  9:36:16 am GMT, Paul Burton <paul.burton@mips.com> wrote:
> Hi Marc,
>
> On Mon, Oct 30, 2017 at 08:00:08AM +0000, Marc Zyngier wrote:
>> >  static int __init gic_of_init(struct device_node *node,
>> >  			      struct device_node *parent)
>> > @@ -768,6 +806,8 @@ static int __init gic_of_init(struct device_node *node,
>> >  		}
>> >  	}
>> >  
>> > -	return 0;
>> > +	return cpuhp_setup_state(CPUHP_AP_IRQ_GIC_STARTING,
>> > +				 "irqchip/mips/gic:starting",
>> > +				 gic_cpu_startup, NULL);
>> 
>> I'm wondering about this. CPUHP_AP_IRQ_GIC_STARTING is a symbol that is
>> used on ARM platforms. You're very welcome to use it (as long as nobody
>> builds a system with both an ARM GIC and a MIPS GIC...), but I'm a bit
>> worried that we could end-up breaking things if one of us decides to
>> reorder it in enum cpuhp_state.
>> 
>> The safest option would be for you to add your own state value, which
>> would allow the two architecture to evolve independently.
>
> I had figured that if something like that ever happens it'd be easy to split
> into 2 states at that point, but sure - I'm happy to add a MIPS-specific state
> now to avoid anyone needing to worry about it.

That would be my preferred option.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny.

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <marc.zyngier@arm.com>
To: Paul Burton <paul.burton@mips.com>
Cc: Jason Cooper <jason@lakedaemon.net>,
	Thomas Gleixner <tglx@linutronix.de>,
	linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/8] irqchip: mips-gic: Use irq_cpu_online to (un)mask all-VP(E) IRQs
Date: Tue, 31 Oct 2017 01:35:02 +0000	[thread overview]
Message-ID: <867evc5cc9.fsf@arm.com> (raw)
Message-ID: <20171031013502.0U1gJAjQ67MLsNDUmValyk9f8DxOz2TVw9Or6QghCok@z> (raw)
In-Reply-To: <20171030163616.tsti7thormxlnxuo@pburton-laptop> (Paul Burton's message of "Mon, 30 Oct 2017 09:36:16 -0700")

On Mon, Oct 30 2017 at  9:36:16 am GMT, Paul Burton <paul.burton@mips.com> wrote:
> Hi Marc,
>
> On Mon, Oct 30, 2017 at 08:00:08AM +0000, Marc Zyngier wrote:
>> >  static int __init gic_of_init(struct device_node *node,
>> >  			      struct device_node *parent)
>> > @@ -768,6 +806,8 @@ static int __init gic_of_init(struct device_node *node,
>> >  		}
>> >  	}
>> >  
>> > -	return 0;
>> > +	return cpuhp_setup_state(CPUHP_AP_IRQ_GIC_STARTING,
>> > +				 "irqchip/mips/gic:starting",
>> > +				 gic_cpu_startup, NULL);
>> 
>> I'm wondering about this. CPUHP_AP_IRQ_GIC_STARTING is a symbol that is
>> used on ARM platforms. You're very welcome to use it (as long as nobody
>> builds a system with both an ARM GIC and a MIPS GIC...), but I'm a bit
>> worried that we could end-up breaking things if one of us decides to
>> reorder it in enum cpuhp_state.
>> 
>> The safest option would be for you to add your own state value, which
>> would allow the two architecture to evolve independently.
>
> I had figured that if something like that ever happens it'd be easy to split
> into 2 states at that point, but sure - I'm happy to add a MIPS-specific state
> now to avoid anyone needing to worry about it.

That would be my preferred option.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny.

  reply	other threads:[~2017-10-31  1:35 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-25 23:37 [PATCH 0/8] irqchip: mips-gic: Cleanups, fixes, prep for multi-cluster Paul Burton
2017-10-25 23:37 ` Paul Burton
2017-10-25 23:37 ` [PATCH 1/8] irqchip: mips-gic: Inline gic_local_irq_domain_map() Paul Burton
2017-10-25 23:37   ` Paul Burton
2017-10-25 23:37 ` [PATCH 2/8] irqchip: mips-gic: Use irq_cpu_online to (un)mask all-VP(E) IRQs Paul Burton
2017-10-25 23:37   ` Paul Burton
2017-10-30  8:00   ` Marc Zyngier
2017-10-30  8:00     ` Marc Zyngier
2017-10-30 16:36     ` Paul Burton
2017-10-30 16:36       ` Paul Burton
2017-10-31  1:35       ` Marc Zyngier [this message]
2017-10-31  1:35         ` Marc Zyngier
2017-10-31 16:41         ` [PATCH v2 0/8] irqchip: mips-gic: Cleanups, fixes, prep for multi-cluster Paul Burton
2017-10-31 16:41           ` Paul Burton
2017-10-31 16:41           ` [PATCH v2 1/8] irqchip: mips-gic: Inline gic_local_irq_domain_map() Paul Burton
2017-10-31 16:41             ` Paul Burton
2017-10-31 16:41           ` [PATCH v2 2/8] irqchip: mips-gic: Use irq_cpu_online to (un)mask all-VP(E) IRQs Paul Burton
2017-10-31 16:41             ` Paul Burton
2017-10-31 16:41           ` [PATCH v2 3/8] irqchip: mips-gic: Mask local interrupts when CPUs come online Paul Burton
2017-10-31 16:41             ` Paul Burton
2017-10-31 16:41           ` [PATCH v2 4/8] irqchip: mips-gic: Configure EIC " Paul Burton
2017-10-31 16:41             ` Paul Burton
2017-10-31 16:41           ` [PATCH v2 5/8] irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs Paul Burton
2017-10-31 16:41             ` Paul Burton
2017-10-31 16:41           ` [PATCH v2 6/8] irqchip: mips-gic: Remove gic_vpes variable Paul Burton
2017-10-31 16:41             ` Paul Burton
2017-10-31 16:41           ` [PATCH v2 7/8] irqchip: mips-gic: Share register writes in gic_set_type() Paul Burton
2017-10-31 16:41             ` Paul Burton
2017-10-31 16:41           ` [PATCH v2 8/8] irqchip: mips-gic: Make IPI bitmaps static Paul Burton
2017-10-31 16:41             ` Paul Burton
2017-11-01  0:13           ` [PATCH v2 0/8] irqchip: mips-gic: Cleanups, fixes, prep for multi-cluster Marc Zyngier
2017-11-01  0:13             ` Marc Zyngier
2017-11-01 16:40             ` Paul Burton
2017-11-01 16:40               ` Paul Burton
2017-11-01 16:59               ` Thomas Gleixner
2017-11-02 10:44                 ` Marc Zyngier
2017-11-02 10:44                   ` Marc Zyngier
2017-10-25 23:37 ` [PATCH 3/8] irqchip: mips-gic: Mask local interrupts when CPUs come online Paul Burton
2017-10-25 23:37   ` Paul Burton
2017-10-25 23:37 ` [PATCH 4/8] irqchip: mips-gic: Configure EIC " Paul Burton
2017-10-25 23:37   ` Paul Burton
2017-10-25 23:37 ` [PATCH 5/8] irqchip: mips-gic: Use num_possible_cpus() to reserve IPIs Paul Burton
2017-10-25 23:37   ` Paul Burton
2017-10-25 23:37 ` [PATCH 6/8] irqchip: mips-gic: Remove gic_vpes variable Paul Burton
2017-10-25 23:37   ` Paul Burton
2017-10-25 23:37 ` [PATCH 7/8] irqchip: mips-gic: Share register writes in gic_set_type() Paul Burton
2017-10-25 23:37   ` Paul Burton
2017-10-25 23:37 ` [PATCH 8/8] irqchip: mips-gic: Make IPI bitmaps static Paul Burton
2017-10-25 23:37   ` Paul Burton

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