From: Marc Zyngier <maz@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Fang Xiang <fangxiang3@xiaomi.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4] irqchip/gic-v3-its: Flush ITS tables before writing GITS_BASER<n> registers in non-coherent GIC designs.
Date: Sun, 05 Nov 2023 09:52:42 +0000 [thread overview]
Message-ID: <86h6m01q8l.wl-maz@kernel.org> (raw)
In-Reply-To: <87bkc8inps.ffs@tglx>
On Sun, 05 Nov 2023 08:55:11 +0000,
Thomas Gleixner <tglx@linutronix.de> wrote:
>
> On Sat, Nov 04 2023 at 09:56, Marc Zyngier wrote:
> > On Mon, 30 Oct 2023 08:32:56 +0000,
> > Fang Xiang <fangxiang3@xiaomi.com> wrote:
> >>
> >> In non-coherent GIC design, ITS tables should be clean and flushed
> >> to the PoV of the ITS before writing GITS_BASER<n> registers, otherwise
> >> the ITS would read dirty tables and lead to UNPREDICTABLE behaviors.
> >>
> >> The ITS always got clean tables in initialization with this fix, by
> >> observing the signals from GIC.
> >>
> >> Furthermore, hoist the quirked non-shareable attributes earlier to
> >> save effort in tables setup.
> >>
> >> Suggested-by: Marc Zyngier <maz@kernel.org>
> >> Signed-off-by: Fang Xiang <fangxiang3@xiaomi.com>
> >> Tested-by: Fang Xiang <fangxiang3@xiaomi.com>
> >
> > Reviewed-by: Marc Zyngier <maz@kernel.org>
>
> Shouldn't this have a Fixes tag? My guess is:
>
> a8707f553884 ("irqchip/gic-v3: Add Rockchip 3588001 erratum workaround")
Yes, that's indeed the point where the out of sequence programming can
occur.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Fang Xiang <fangxiang3@xiaomi.com>,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4] irqchip/gic-v3-its: Flush ITS tables before writing GITS_BASER<n> registers in non-coherent GIC designs.
Date: Sun, 05 Nov 2023 09:52:42 +0000 [thread overview]
Message-ID: <86h6m01q8l.wl-maz@kernel.org> (raw)
In-Reply-To: <87bkc8inps.ffs@tglx>
On Sun, 05 Nov 2023 08:55:11 +0000,
Thomas Gleixner <tglx@linutronix.de> wrote:
>
> On Sat, Nov 04 2023 at 09:56, Marc Zyngier wrote:
> > On Mon, 30 Oct 2023 08:32:56 +0000,
> > Fang Xiang <fangxiang3@xiaomi.com> wrote:
> >>
> >> In non-coherent GIC design, ITS tables should be clean and flushed
> >> to the PoV of the ITS before writing GITS_BASER<n> registers, otherwise
> >> the ITS would read dirty tables and lead to UNPREDICTABLE behaviors.
> >>
> >> The ITS always got clean tables in initialization with this fix, by
> >> observing the signals from GIC.
> >>
> >> Furthermore, hoist the quirked non-shareable attributes earlier to
> >> save effort in tables setup.
> >>
> >> Suggested-by: Marc Zyngier <maz@kernel.org>
> >> Signed-off-by: Fang Xiang <fangxiang3@xiaomi.com>
> >> Tested-by: Fang Xiang <fangxiang3@xiaomi.com>
> >
> > Reviewed-by: Marc Zyngier <maz@kernel.org>
>
> Shouldn't this have a Fixes tag? My guess is:
>
> a8707f553884 ("irqchip/gic-v3: Add Rockchip 3588001 erratum workaround")
Yes, that's indeed the point where the out of sequence programming can
occur.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2023-11-05 9:53 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-30 8:32 [PATCH v4] irqchip/gic-v3-its: Flush ITS tables before writing GITS_BASER<n> registers in non-coherent GIC designs Fang Xiang
2023-10-30 8:32 ` Fang Xiang
2023-11-04 9:56 ` Marc Zyngier
2023-11-04 9:56 ` Marc Zyngier
2023-11-05 8:55 ` Thomas Gleixner
2023-11-05 8:55 ` Thomas Gleixner
2023-11-05 9:52 ` Marc Zyngier [this message]
2023-11-05 9:52 ` Marc Zyngier
2023-11-06 0:28 ` [tip: irq/urgent] irqchip/gic-v3-its: Flush ITS tables correctly " tip-bot2 for Fang Xiang
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