From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [RFC PATCH] arm/arm64: KVM: Fix BE accesses to GICv2 EISR and ELRSR regs
Date: Tue, 14 Oct 2014 10:47:34 +0100 [thread overview]
Message-ID: <86k343geyx.fsf@arm.com> (raw)
In-Reply-To: <1411913066-3787-1-git-send-email-christoffer.dall@linaro.org> (Christoffer Dall's message of "Sun, 28 Sep 2014 15:04:26 +0100")
On Sun, Sep 28 2014 at 03:04:26 PM, Christoffer Dall <christoffer.dall@linaro.org> wrote:
> The EIRSR and ELRSR registers are 32-bit registers on GICv2, and we
> store these as an array of two such registers on the vgic vcpu struct.
> However, we access them as a single 64-bit value or as a bitmap pointer
> in the generic vgic code, which breaks BE support.
>
> Instead, store them as u64 values on the vgic structure and do the
> word-swapping in the assembly code, which already handles the byte order
> for BE systems.
>
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(still going through my email backlog, hence the delay).
This looks like a valuable fix. Haven't had a chance to try it (no BE
setup at hand) but maybe Victor can help reproducing this?.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead. It just smells funny.
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <marc.zyngier@arm.com>
To: Christoffer Dall <christoffer.dall@linaro.org>
Cc: "kvmarm\@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>,
"kvm\@vger.kernel.org" <kvm@vger.kernel.org>,
"linux-arm-kernel\@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [RFC PATCH] arm/arm64: KVM: Fix BE accesses to GICv2 EISR and ELRSR regs
Date: Tue, 14 Oct 2014 10:47:34 +0100 [thread overview]
Message-ID: <86k343geyx.fsf@arm.com> (raw)
In-Reply-To: <1411913066-3787-1-git-send-email-christoffer.dall@linaro.org> (Christoffer Dall's message of "Sun, 28 Sep 2014 15:04:26 +0100")
On Sun, Sep 28 2014 at 03:04:26 PM, Christoffer Dall <christoffer.dall@linaro.org> wrote:
> The EIRSR and ELRSR registers are 32-bit registers on GICv2, and we
> store these as an array of two such registers on the vgic vcpu struct.
> However, we access them as a single 64-bit value or as a bitmap pointer
> in the generic vgic code, which breaks BE support.
>
> Instead, store them as u64 values on the vgic structure and do the
> word-swapping in the assembly code, which already handles the byte order
> for BE systems.
>
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
(still going through my email backlog, hence the delay).
This looks like a valuable fix. Haven't had a chance to try it (no BE
setup at hand) but maybe Victor can help reproducing this?.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead. It just smells funny.
next prev parent reply other threads:[~2014-10-14 9:47 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-28 14:04 [RFC PATCH] arm/arm64: KVM: Fix BE accesses to GICv2 EISR and ELRSR regs Christoffer Dall
2014-09-28 14:04 ` Christoffer Dall
2014-10-01 16:55 ` Andre Przywara
2014-10-01 16:55 ` Andre Przywara
2014-10-01 17:45 ` Christoffer Dall
2014-10-01 17:45 ` Christoffer Dall
2014-10-14 9:47 ` Marc Zyngier [this message]
2014-10-14 9:47 ` Marc Zyngier
2014-10-14 15:21 ` Victor Kamensky
2014-10-14 15:21 ` Victor Kamensky
2014-10-15 23:54 ` Victor Kamensky
2014-10-15 23:54 ` Victor Kamensky
2014-10-16 8:48 ` Christoffer Dall
2014-10-16 8:48 ` Christoffer Dall
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