From: Torbjorn Granlund <tg@gmplib.org>
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] [Qemu-ppc] Incorrect handling of more PPC64 insns (PATCH)
Date: Wed, 08 May 2013 11:20:48 +0200 [thread overview]
Message-ID: <86k3n9omj3.fsf@shell.gmplib.org> (raw)
In-Reply-To: <20130508065009.GP5000@ohm.aurel32.net> (Aurelien Jarno's message of "Wed\, 8 May 2013 08\:50\:09 +0200")
Aurelien Jarno <aurelien@aurel32.net> writes:
64-bit CPUs check for the L bit of comparison instruction to determine
if the instruction is 32-bit wide, and not to the MSR SF bit.
L=1 on a 32-bit CPU should generate an invalid instruction exception.
No. See my previous post.
The L bit is to be ignored for 32-bit CPUs, just like the original code
did.
--
Torbjörn
next prev parent reply other threads:[~2013-05-08 9:21 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-06 17:00 [Qemu-devel] Incorrect handling of PPC64 rldcl insn Torbjorn Granlund
2013-05-06 17:47 ` Alexander Graf
2013-05-06 18:13 ` Torbjorn Granlund
2013-05-06 22:14 ` Alexander Graf
2013-05-06 23:12 ` Aurelien Jarno
2013-05-07 10:27 ` [Qemu-devel] Incorrect handling of more PPC64 insns Torbjorn Granlund
2013-05-07 10:39 ` Peter Maydell
2013-05-07 11:48 ` Torbjorn Granlund
2013-05-07 11:51 ` Peter Maydell
2013-05-07 15:58 ` [Qemu-devel] Incorrect handling of more PPC64 insns (PATCH) Torbjorn Granlund
2013-05-07 17:12 ` [Qemu-devel] [Qemu-ppc] " Alexander Graf
2013-05-07 18:10 ` Torbjorn Granlund
2013-05-07 19:30 ` Torbjorn Granlund
2013-05-07 22:00 ` Alexander Graf
2013-05-08 6:50 ` Aurelien Jarno
2013-05-08 6:52 ` Alexander Graf
2013-05-08 9:20 ` Torbjorn Granlund [this message]
2013-05-08 9:32 ` Alexander Graf
2013-05-08 9:57 ` Alexander Graf
2013-05-08 10:07 ` Torbjorn Granlund
2013-05-08 10:45 ` Alexander Graf
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