From: Marc Zyngier <maz@kernel.org>
To: Oliver Upton <oliver.upton@linux.dev>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org, Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Zenghui Yu <yuzenghui@huawei.com>,
Peter Maydell <peter.maydell@linaro.org>,
stable@vger.kernel.org
Subject: Re: [PATCH 1/3] KVM: arm64: Make ID_PFR1_EL1.GIC writable
Date: Thu, 30 Oct 2025 11:25:17 +0000 [thread overview]
Message-ID: <86tszgvdgi.wl-maz@kernel.org> (raw)
In-Reply-To: <aPiBH1_WZicoE7Od@linux.dev>
On Wed, 22 Oct 2025 08:00:47 +0100,
Oliver Upton <oliver.upton@linux.dev> wrote:
>
> Hey,
>
> On Mon, Oct 13, 2025 at 09:32:05AM +0100, Marc Zyngier wrote:
> > Similarly to ID_AA64PFR0_EL1.GIC, relax ID_PFR1_EL1.GIC to be writable.
>
> This looks fine to me, although I do wonder if we should just allow
> userspace to write whatever value it wants to the 32-bit ID registers
> and be done with it.
That's a good point. Nobody really cares about 32bit anyway, and I'd
be happy to just let the VMM write whatever it wants. Might be a bit
harder to backport, but whoever is interested in AArch32 will be able
to do it.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2025-10-30 11:25 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-13 8:32 [PATCH 0/3] KVM: arm64: Fix handling of ID_PFR1_EL1.GIC Marc Zyngier
2025-10-13 8:32 ` [PATCH 1/3] KVM: arm64: Make ID_PFR1_EL1.GIC writable Marc Zyngier
2025-10-22 7:00 ` Oliver Upton
2025-10-30 11:25 ` Marc Zyngier [this message]
2025-10-13 8:32 ` [PATCH 2/3] KVM: arm64: Set ID_{AA64PFR0,PFR1}_EL1.GIC when GICv3 is configured Marc Zyngier
2025-10-22 7:04 ` Oliver Upton
2025-10-13 8:32 ` [PATCH 3/3] KVM: arm64: Limit clearing of ID_{AA64PFR0,PFR1}_EL1.GIC to userspace irqchip Marc Zyngier
2025-10-22 7:08 ` Oliver Upton
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