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From: Oliver Upton <oliver.upton@linux.dev>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	kvm@vger.kernel.org, Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	stable@vger.kernel.org
Subject: Re: [PATCH 1/3] KVM: arm64: Make ID_PFR1_EL1.GIC writable
Date: Wed, 22 Oct 2025 00:00:47 -0700	[thread overview]
Message-ID: <aPiBH1_WZicoE7Od@linux.dev> (raw)
In-Reply-To: <20251013083207.518998-2-maz@kernel.org>

Hey,

On Mon, Oct 13, 2025 at 09:32:05AM +0100, Marc Zyngier wrote:
> Similarly to ID_AA64PFR0_EL1.GIC, relax ID_PFR1_EL1.GIC to be writable.

This looks fine to me, although I do wonder if we should just allow
userspace to write whatever value it wants to the 32-bit ID registers
and be done with it.

Nowhere do we use a 32-bit ID register value as a condition for trap
configuration / emulation, so even if the VMM lies to the guest it
shouldn't trip up KVM.

Thanks,
Oliver

  reply	other threads:[~2025-10-22  7:01 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-13  8:32 [PATCH 0/3] KVM: arm64: Fix handling of ID_PFR1_EL1.GIC Marc Zyngier
2025-10-13  8:32 ` [PATCH 1/3] KVM: arm64: Make ID_PFR1_EL1.GIC writable Marc Zyngier
2025-10-22  7:00   ` Oliver Upton [this message]
2025-10-30 11:25     ` Marc Zyngier
2025-10-13  8:32 ` [PATCH 2/3] KVM: arm64: Set ID_{AA64PFR0,PFR1}_EL1.GIC when GICv3 is configured Marc Zyngier
2025-10-22  7:04   ` Oliver Upton
2025-10-13  8:32 ` [PATCH 3/3] KVM: arm64: Limit clearing of ID_{AA64PFR0,PFR1}_EL1.GIC to userspace irqchip Marc Zyngier
2025-10-22  7:08   ` Oliver Upton

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