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From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3] irqchip/gic-v3: Ensure GICR_CTLR.EnableLPI=0 is observed before enabling
Date: Tue, 19 Jun 2018 15:46:35 +0100	[thread overview]
Message-ID: <86tvpy7s1g.wl-marc.zyngier@arm.com> (raw)
In-Reply-To: <8898674D84E3B24BA3A2D289B872026A69F37935@G01JPEXMBKW03>

Hi Lei,

On Tue, 19 Jun 2018 15:14:27 +0100,
"Zhang, Lei" <zhang.lei@jp.fujitsu.com> wrote:
> 
> Hi shankerd, Marc
> 
> I have one question.
> 
> Does it means after GICR_CTLR.EnableLPI has been written to 1, 
> if the bit GICR_CTLR.EnableLPI becomes RES1, we can't use LPIs?
> Because its_cpu_init_lpis and its_cpu_init_collections will not be called. 

There are two issues:

- If EnableLPI is already set to 1, your redistributors are already
  potentially corrupting the memory by writing to the pending
  tables. Your system is now potentially unstable (single bit
  corruption, depending on what the ITS outputs).

- If EnableLPI has become RES1, you cannot even turn it off to
  reprogram things so that the property and pending tables are under
  your control.

At that stage, your system is in a very bad shape, and LPIs are the
least of your problems.

Thanks,

	M.

-- 
Jazz is not dead, it just smell funny.

  reply	other threads:[~2018-06-19 14:46 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-22  1:58 [PATCH v3] irqchip/gic-v3: Ensure GICR_CTLR.EnableLPI=0 is observed before enabling Shanker Donthineni
2018-03-22  1:58 ` Shanker Donthineni
2018-03-22 15:51 ` Marc Zyngier
2018-03-22 15:51   ` Marc Zyngier
2018-03-22 19:41   ` Shanker Donthineni
2018-03-22 19:41     ` Shanker Donthineni
2018-03-23  9:19     ` Marc Zyngier
2018-03-23  9:19       ` Marc Zyngier
2018-06-19 14:14       ` Zhang, Lei
2018-06-19 14:46         ` Marc Zyngier [this message]
2018-06-21 10:57           ` Zhang, Lei
2018-06-21 12:02             ` Marc Zyngier
2018-06-26 14:53               ` Marc Zyngier

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