diff for duplicates of <86tvz2ksl3.fsf@arm.com> diff --git a/a/1.txt b/N1/1.txt index dc99a9c..6960563 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,11 +1,11 @@ -On Fri, Oct 13 2017 at 1:50:06 pm BST, Rob Herring <robh+dt@kernel.org> wrote: -> On Fri, Oct 13, 2017 at 4:47 AM, Marc Zyngier <marc.zyngier@arm.com> wrote: +On Fri, Oct 13 2017 at 1:50:06 pm BST, Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote: +> On Fri, Oct 13, 2017 at 4:47 AM, Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> wrote: >> [+Mark] >> >> On 12/10/17 23:24, Ard Biesheuvel wrote: ->>> On 12 October 2017 at 22:34, Rob Herring <robh+dt@kernel.org> wrote: +>>> On 12 October 2017 at 22:34, Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote: >>>> On Thu, Oct 12, 2017 at 1:32 PM, Ard Biesheuvel ->>>> <ard.biesheuvel@linaro.org> wrote: +>>>> <ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote: >>>>> The Socionext Synquacer SoC's implementation of GICv3 has a so-called >>>>> 'pre-ITS', which maps 32-bit writes targeted at a separate window of >>>>> size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device @@ -16,7 +16,7 @@ On Fri, Oct 13 2017 at 1:50:06 pm BST, Rob Herring <robh+dt@kernel.org> wrote: >>>>> So add a workaround for this. Given that this breaks isolation, clear >>>>> the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well. >>>>> ->>>>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> +>>>>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> >>>>> --- >>>>> Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 4 ++ >>>>> arch/arm64/Kconfig | 8 +++ @@ -45,11 +45,11 @@ On Fri, Oct 13 2017 at 1:50:06 pm BST, Rob Herring <robh+dt@kernel.org> wrote: >>> >>> For my understanding, you mean either >>> ->>> gic: interrupt-controller at 30000000 { +>>> gic: interrupt-controller@30000000 { >>> compatible = "arm,gic-v3"; >>> ... >>> ->>> its: gic-its at 30020000 { +>>> its: gic-its@30020000 { >>> compatible = "arm,gic-v3-its"; >>> reg = <0x0 0x30020000 0x0 0x20000>; >>> #msi-cells = <1>; @@ -57,7 +57,7 @@ On Fri, Oct 13 2017 at 1:50:06 pm BST, Rob Herring <robh+dt@kernel.org> wrote: >>> }; >>> }; >>> ->>> preits at 58000000 { +>>> preits@58000000 { >>> compatible = "socionext,synquacer-pre-its"; >>> reg = <0x0 0x58000000 0x0 0x200000>; >>> msi-slave = <&its>; @@ -65,11 +65,11 @@ On Fri, Oct 13 2017 at 1:50:06 pm BST, Rob Herring <robh+dt@kernel.org> wrote: >>> >>> or >>> ->>> gic: interrupt-controller at 30000000 { +>>> gic: interrupt-controller@30000000 { >>> compatible = "arm,gic-v3"; >>> ... >>> ->>> its: gic-its at 30020000 { +>>> its: gic-its@30020000 { >>> compatible = "socionext,synquacer-pre-its", "arm,gic-v3-its"; >>> reg = <0x0 0x30020000 0x0 0x20000>, >>> <0x0 0x58000000 0x0 0x200000>; @@ -113,3 +113,7 @@ Thanks, M. -- Jazz is not dead. It just smells funny. +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 825b843..6dfb08d 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -4,20 +4,31 @@ "ref\0CAKv+Gu-rZNhMMU4PoD8V0nBtwEEu+HE71wvaAZk2PWshoeTi4g@mail.gmail.com\0" "ref\0c6c00e64-ecc8-0404-5ffc-602626e5cc6d@arm.com\0" "ref\0CAL_Jsq+dsEW3M374e_ivwcBnk7s8rQToagWLx3EsBof8bK__JQ@mail.gmail.com\0" - "From\0marc.zyngier@arm.com (Marc Zyngier)\0" - "Subject\0[PATCH v3 2/2] drivers/irqchip: gicv3: add workaround for Synquacer pre-ITS\0" + "ref\0CAL_Jsq+dsEW3M374e_ivwcBnk7s8rQToagWLx3EsBof8bK__JQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0" + "From\0Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>\0" + "Subject\0Re: [PATCH v3 2/2] drivers/irqchip: gicv3: add workaround for Synquacer pre-ITS\0" "Date\0Sat, 14 Oct 2017 10:05:12 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\0" + "Cc\0Ard Biesheuvel <ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>" + Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> + Daniel Thompson <daniel.thompson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + Leif Lindholm <leif.lindholm-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + Graeme Gregory <graeme.gregory-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> + Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> + Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> + devicetree@vger.kernel.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> + " Mark Rutland <Mark.Rutland-5wv7dgnIgG8@public.gmane.org>\0" "\00:1\0" "b\0" - "On Fri, Oct 13 2017 at 1:50:06 pm BST, Rob Herring <robh+dt@kernel.org> wrote:\n" - "> On Fri, Oct 13, 2017 at 4:47 AM, Marc Zyngier <marc.zyngier@arm.com> wrote:\n" + "On Fri, Oct 13 2017 at 1:50:06 pm BST, Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:\n" + "> On Fri, Oct 13, 2017 at 4:47 AM, Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org> wrote:\n" ">> [+Mark]\n" ">>\n" ">> On 12/10/17 23:24, Ard Biesheuvel wrote:\n" - ">>> On 12 October 2017 at 22:34, Rob Herring <robh+dt@kernel.org> wrote:\n" + ">>> On 12 October 2017 at 22:34, Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:\n" ">>>> On Thu, Oct 12, 2017 at 1:32 PM, Ard Biesheuvel\n" - ">>>> <ard.biesheuvel@linaro.org> wrote:\n" + ">>>> <ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:\n" ">>>>> The Socionext Synquacer SoC's implementation of GICv3 has a so-called\n" ">>>>> 'pre-ITS', which maps 32-bit writes targeted at a separate window of\n" ">>>>> size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device\n" @@ -28,7 +39,7 @@ ">>>>> So add a workaround for this. Given that this breaks isolation, clear\n" ">>>>> the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well.\n" ">>>>>\n" - ">>>>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>\n" + ">>>>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>\n" ">>>>> ---\n" ">>>>> Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 4 ++\n" ">>>>> arch/arm64/Kconfig | 8 +++\n" @@ -57,11 +68,11 @@ ">>>\n" ">>> For my understanding, you mean either\n" ">>>\n" - ">>> gic: interrupt-controller at 30000000 {\n" + ">>> gic: interrupt-controller@30000000 {\n" ">>> compatible = \"arm,gic-v3\";\n" ">>> ...\n" ">>>\n" - ">>> its: gic-its at 30020000 {\n" + ">>> its: gic-its@30020000 {\n" ">>> compatible = \"arm,gic-v3-its\";\n" ">>> reg = <0x0 0x30020000 0x0 0x20000>;\n" ">>> #msi-cells = <1>;\n" @@ -69,7 +80,7 @@ ">>> };\n" ">>> };\n" ">>>\n" - ">>> preits at 58000000 {\n" + ">>> preits@58000000 {\n" ">>> compatible = \"socionext,synquacer-pre-its\";\n" ">>> reg = <0x0 0x58000000 0x0 0x200000>;\n" ">>> msi-slave = <&its>;\n" @@ -77,11 +88,11 @@ ">>>\n" ">>> or\n" ">>>\n" - ">>> gic: interrupt-controller at 30000000 {\n" + ">>> gic: interrupt-controller@30000000 {\n" ">>> compatible = \"arm,gic-v3\";\n" ">>> ...\n" ">>>\n" - ">>> its: gic-its at 30020000 {\n" + ">>> its: gic-its@30020000 {\n" ">>> compatible = \"socionext,synquacer-pre-its\", \"arm,gic-v3-its\";\n" ">>> reg = <0x0 0x30020000 0x0 0x20000>,\n" ">>> <0x0 0x58000000 0x0 0x200000>;\n" @@ -124,6 +135,10 @@ "\n" "\tM.\n" "-- \n" - Jazz is not dead. It just smells funny. + "Jazz is not dead. It just smells funny.\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -898d298df86553a2b350e83eeace7c912af62c2b1bdc58172638a17a46860a08 +a7d23c7c368bd191f5d2cc7b22e5b4b3adf6f41d8d7eb36bd39f9a11f037a242
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